Simulation Results: clkmgr

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.55 %
  • code
  • 98.26 %
  • assert
  • 95.76 %
  • func
  • 86.62 %
  • line
  • 99.00 %
  • branch
  • 98.59 %
  • cond
  • 94.52 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.830s 17.804us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.730s 28.034us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.980s 210.881us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 9.370s 2456.726us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.390s 63.438us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.790s 36.254us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.980s 210.881us 1 1 100.00
clkmgr_csr_aliasing 1.390s 63.438us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.760s 16.212us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.920s 98.093us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.850s 50.807us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.770s 19.322us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.830s 17.804us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 1.560s 203.751us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.270s 1222.534us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 1.560s 203.751us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 1.660s 273.692us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.730s 30.990us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.420s 60.045us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.420s 60.045us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.730s 28.034us 1 1 100.00
clkmgr_csr_rw 0.980s 210.881us 1 1 100.00
clkmgr_csr_aliasing 1.390s 63.438us 1 1 100.00
clkmgr_same_csr_outstanding 0.850s 38.536us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.730s 28.034us 1 1 100.00
clkmgr_csr_rw 0.980s 210.881us 1 1 100.00
clkmgr_csr_aliasing 1.390s 63.438us 1 1 100.00
clkmgr_same_csr_outstanding 0.850s 38.536us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 32.680s 10016.530us 0 1 0.00
clkmgr_tl_intg_err 1.280s 77.293us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.040s 88.293us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.040s 88.293us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.040s 88.293us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.040s 88.293us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 7.760s 2421.291us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.280s 77.293us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 1.560s 203.751us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.270s 1222.534us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.040s 88.293us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.830s 22.867us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.980s 86.046us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.740s 48.033us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.840s 17.101us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.670s 34.249us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.980s 210.881us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 32.680s 10016.530us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.980s 210.881us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.980s 210.881us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 32.680s 10016.530us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.080s 171.524us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 44.370s 14571.943us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_hints (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 45237957882773334796000152254852040938044914143748561211181573577310072084059 76
UVM_INFO @ 2421290734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 98401025139951259216571785740776411521916960021882584337514780893809610197335 85
UVM_INFO @ 10016529955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---