Simulation Results: edn/edn0

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.57 %
  • code
  • 84.90 %
  • assert
  • 98.26 %
  • func
  • 79.56 %
  • line
  • 98.10 %
  • branch
  • 93.86 %
  • cond
  • 88.04 %
  • toggle
  • 92.33 %
  • FSM
  • 52.15 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.880s 49.984us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.880s 207.051us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 41.116us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.260s 1717.408us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.960s 16.606us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.210s 47.797us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 41.116us 1 1 100.00
edn_csr_aliasing 0.960s 16.606us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.330s 68.486us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.330s 68.486us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.330s 68.486us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.930s 29.334us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.960s 109.664us 1 1 100.00
errs 1 1 100.00
edn_err 1.080s 46.079us 1 1 100.00
disable 2 2 100.00
edn_disable 0.840s 14.074us 1 1 100.00
edn_disable_auto_req_mode 1.210s 52.931us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.620s 512.592us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.810s 23.118us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.870s 50.919us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.850s 147.200us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.850s 147.200us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.880s 207.051us 1 1 100.00
edn_csr_rw 0.770s 41.116us 1 1 100.00
edn_csr_aliasing 0.960s 16.606us 1 1 100.00
edn_same_csr_outstanding 0.900s 22.812us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.880s 207.051us 1 1 100.00
edn_csr_rw 0.770s 41.116us 1 1 100.00
edn_csr_aliasing 0.960s 16.606us 1 1 100.00
edn_same_csr_outstanding 0.900s 22.812us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.910s 3157.349us 1 1 100.00
edn_tl_intg_err 1.630s 291.092us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.850s 30.839us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.960s 109.664us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.910s 3157.349us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.910s 3157.349us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.910s 3157.349us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.910s 3157.349us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.960s 109.664us 1 1 100.00
edn_sec_cm 5.910s 3157.349us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.960s 109.664us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.630s 291.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 2.260s 50.229us 1 1 100.00