Simulation Results: edn/edn1

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.81 %
  • code
  • 81.10 %
  • assert
  • 98.44 %
  • func
  • 80.88 %
  • line
  • 97.80 %
  • branch
  • 92.64 %
  • cond
  • 89.31 %
  • toggle
  • 87.10 %
  • FSM
  • 38.64 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.750s 17.942us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.760s 53.819us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.730s 14.831us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.370s 273.661us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.010s 34.246us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.880s 210.881us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.730s 14.831us 1 1 100.00
edn_csr_aliasing 1.010s 34.246us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.920s 96.111us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.920s 96.111us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.920s 96.111us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.780s 140.630us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.980s 59.499us 1 1 100.00
errs 1 1 100.00
edn_err 0.920s 42.452us 1 1 100.00
disable 2 2 100.00
edn_disable 0.780s 13.405us 1 1 100.00
edn_disable_auto_req_mode 0.890s 29.931us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.600s 322.478us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.850s 35.801us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.690s 37.342us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.170s 25.560us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.170s 25.560us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.760s 53.819us 1 1 100.00
edn_csr_rw 0.730s 14.831us 1 1 100.00
edn_csr_aliasing 1.010s 34.246us 1 1 100.00
edn_same_csr_outstanding 0.890s 16.161us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.760s 53.819us 1 1 100.00
edn_csr_rw 0.730s 14.831us 1 1 100.00
edn_csr_aliasing 1.010s 34.246us 1 1 100.00
edn_same_csr_outstanding 0.890s 16.161us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.260s 338.901us 1 1 100.00
edn_tl_intg_err 1.280s 80.929us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.740s 39.755us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.980s 59.499us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.260s 338.901us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.260s 338.901us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.260s 338.901us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.260s 338.901us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.980s 59.499us 1 1 100.00
edn_sec_cm 2.260s 338.901us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.980s 59.499us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.280s 80.929us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 43.150s 6678.356us 1 1 100.00