Simulation Results: flash_ctrl

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.33 %
  • code
  • 93.00 %
  • assert
  • 94.64 %
  • func
  • 95.36 %
  • line
  • 95.88 %
  • branch
  • 96.62 %
  • cond
  • 93.31 %
  • toggle
  • 94.84 %
  • FSM
  • 84.35 %
Validation stages
V1
100.00%
V2
98.28%
V2S
95.83%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 70.580s 140.286us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 10.790s 113.159us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 20.240s 130.161us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 6.230s 76.755us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 29.000s 8301.057us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 20.460s 829.927us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 7.250s 103.103us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 6.230s 76.755us 1 1 100.00
flash_ctrl_csr_aliasing 20.460s 829.927us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.510s 100.674us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.760s 35.250us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.860s 55.895us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 47.060s 79.347us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1089.240s 93867.851us 1 1 100.00
flash_ctrl_hw_rma_reset 476.050s 110162.580us 1 1 100.00
flash_ctrl_lcmgr_intg 5.630s 72.284us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1349.400s 244840.596us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 230.840s 8007.719us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.630s 37.274us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1591.820s 111873.593us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 44.920s 749.888us 1 1 100.00
rd_buff_eviction_w_ecc 2 3 66.67
flash_ctrl_rw_evict 13.770s 49.812us 1 1 100.00
flash_ctrl_rw_evict_all_en 13.450s 96.061us 0 1 0.00
flash_ctrl_re_evict 16.470s 108.868us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 170.290s 11172.595us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 170.290s 11172.595us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 141.720s 10459.328us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 15.080s 3367.620us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 355.980s 208.285us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 334.660s 6931.367us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 283.930s 784.243us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 1085.000s 4404.628us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.720s 23.164us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 146.560s 2274.723us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.950s 69.559us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 6.160s 64.513us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 78.240s 47.962us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 123.290s 6143.115us 1 1 100.00
flash_ctrl_otp_reset 53.930s 195.005us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1089.240s 93867.851us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 67.560s 1011.728us 1 1 100.00
flash_ctrl_intr_wr 44.230s 5303.834us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 122.590s 8987.744us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 123.750s 50382.732us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 34.150s 4110.013us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 32.970s 2031.897us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 10.190s 57.558us 1 1 100.00
flash_ctrl_ro_derr 90.930s 1053.339us 1 1 100.00
flash_ctrl_rw_derr 130.590s 5351.888us 1 1 100.00
flash_ctrl_derr_detect 89.830s 8220.721us 1 1 100.00
flash_ctrl_integrity 328.230s 17183.590us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 9.990s 54.931us 1 1 100.00
flash_ctrl_ro_serr 83.420s 2604.761us 1 1 100.00
flash_ctrl_rw_serr 114.510s 7097.367us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 41.850s 1906.825us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 39.250s 3589.689us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 81.050s 2475.203us 1 1 100.00
flash_ctrl_write_word_sweep 6.340s 43.451us 1 1 100.00
flash_ctrl_read_word_sweep 6.130s 39.358us 1 1 100.00
flash_ctrl_ro 79.360s 903.898us 1 1 100.00
flash_ctrl_rw 264.000s 3656.319us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 20.370s 401.893us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 515.670s 42235.339us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 63.760s 10024.231us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.290s 124.624us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.100s 29.262us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.530s 64.688us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.530s 64.688us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.240s 130.161us 1 1 100.00
flash_ctrl_csr_rw 6.230s 76.755us 1 1 100.00
flash_ctrl_csr_aliasing 20.460s 829.927us 1 1 100.00
flash_ctrl_same_csr_outstanding 6.580s 402.078us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.240s 130.161us 1 1 100.00
flash_ctrl_csr_rw 6.230s 76.755us 1 1 100.00
flash_ctrl_csr_aliasing 20.460s 829.927us 1 1 100.00
flash_ctrl_same_csr_outstanding 6.580s 402.078us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 10.070s 37.399us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 10.070s 37.399us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 10.070s 37.399us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 10.070s 37.399us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 7.220s 190.758us 1 1 100.00
tl_intg_err 1 2 50.00
flash_ctrl_sec_cm 1140.810s 1450.745us 0 1 0.00
flash_ctrl_tl_intg_err 143.670s 751.610us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 143.670s 751.610us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 143.670s 751.610us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.710s 247.372us 1 1 100.00
flash_ctrl_wr_intg 6.840s 50.943us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 70.580s 140.286us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 53.930s 195.005us 1 1 100.00
flash_ctrl_disable 9.950s 69.559us 1 1 100.00
flash_ctrl_sec_info_access 41.920s 8955.089us 1 1 100.00
flash_ctrl_connect 6.160s 64.513us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.010s 80.076us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.230s 76.755us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 10.070s 37.399us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.230s 76.755us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 10.070s 37.399us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.230s 76.755us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 10.070s 37.399us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.950s 69.559us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.710s 247.372us 1 1 100.00
flash_ctrl_access_after_disable 6.220s 41.119us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 14.030s 28.253us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.950s 69.559us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 15.080s 3367.620us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 264.000s 3656.319us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 114.510s 7097.367us 1 1 100.00
flash_ctrl_rw_derr 130.590s 5351.888us 1 1 100.00
flash_ctrl_integrity 328.230s 17183.590us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1089.240s 93867.851us 1 1 100.00
sec_cm_ctrl_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 1140.810s 1450.745us 0 1 0.00
sec_cm_phy_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 1140.810s 1450.745us 0 1 0.00
sec_cm_phy_prog_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 1140.810s 1450.745us 0 1 0.00
sec_cm_ctr_redun 0 1 0.00
flash_ctrl_sec_cm 1140.810s 1450.745us 0 1 0.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 8.530s 892.184us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 5.770s 43.744us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.090s 102.018us 1 1 100.00
sec_cm_fifo_ctr_redun 0 1 0.00
flash_ctrl_sec_cm 1140.810s 1450.745us 0 1 0.00
sec_cm_mem_tl_lc_gate_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 1140.810s 1450.745us 0 1 0.00
sec_cm_prog_tl_lc_gate_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 1140.810s 1450.745us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 19.380s 270.285us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 27.550s 229.066us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * 1 test run
flash_ctrl_rw_evict_all_en 74837285644494816938967569546534807573693533273350004727860873601737427024366 113
UVM_INFO @ 96060.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_receiver_driver.sv:262) driver [driver] m_transaction_tasks nonempty after reset: '{*:*} 1 test run
flash_ctrl_sec_cm 110391326761666611813974615181304488107259255080684838573226169468227921397109 4995
UVM_INFO @ 1450745.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---