Simulation Results: hmac

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.86 %
  • code
  • 97.80 %
  • assert
  • 97.60 %
  • func
  • 44.18 %
  • line
  • 99.74 %
  • branch
  • 99.17 %
  • cond
  • 95.96 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.980s 352.667us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.860s 37.990us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.730s 26.643us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.980s 878.846us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 1.950s 227.651us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 587.810s 285615.048us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.730s 26.643us 1 1 100.00
hmac_csr_aliasing 1.950s 227.651us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 36.100s 1426.304us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 29.230s 1051.492us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 7.790s 247.721us 1 1 100.00
hmac_test_sha384_vectors 18.900s 1375.453us 1 1 100.00
hmac_test_sha512_vectors 18.810s 1286.187us 1 1 100.00
hmac_test_hmac256_vectors 8.380s 3054.021us 1 1 100.00
hmac_test_hmac384_vectors 10.790s 519.096us 1 1 100.00
hmac_test_hmac512_vectors 8.990s 1561.576us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 7.630s 278.294us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 606.540s 7154.748us 1 1 100.00
error 1 1 100.00
hmac_error 26.810s 6969.637us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 84.400s 3534.914us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.980s 352.667us 1 1 100.00
hmac_long_msg 36.100s 1426.304us 1 1 100.00
hmac_back_pressure 29.230s 1051.492us 1 1 100.00
hmac_datapath_stress 606.540s 7154.748us 1 1 100.00
hmac_burst_wr 7.630s 278.294us 1 1 100.00
hmac_stress_all 34.140s 5117.359us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.980s 352.667us 1 1 100.00
hmac_long_msg 36.100s 1426.304us 1 1 100.00
hmac_back_pressure 29.230s 1051.492us 1 1 100.00
hmac_datapath_stress 606.540s 7154.748us 1 1 100.00
hmac_wipe_secret 84.400s 3534.914us 1 1 100.00
hmac_test_sha256_vectors 7.790s 247.721us 1 1 100.00
hmac_test_sha384_vectors 18.900s 1375.453us 1 1 100.00
hmac_test_sha512_vectors 18.810s 1286.187us 1 1 100.00
hmac_test_hmac256_vectors 8.380s 3054.021us 1 1 100.00
hmac_test_hmac384_vectors 10.790s 519.096us 1 1 100.00
hmac_test_hmac512_vectors 8.990s 1561.576us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.980s 352.667us 1 1 100.00
hmac_long_msg 36.100s 1426.304us 1 1 100.00
hmac_back_pressure 29.230s 1051.492us 1 1 100.00
hmac_datapath_stress 606.540s 7154.748us 1 1 100.00
hmac_burst_wr 7.630s 278.294us 1 1 100.00
hmac_error 26.810s 6969.637us 1 1 100.00
hmac_wipe_secret 84.400s 3534.914us 1 1 100.00
hmac_test_sha256_vectors 7.790s 247.721us 1 1 100.00
hmac_test_sha384_vectors 18.900s 1375.453us 1 1 100.00
hmac_test_sha512_vectors 18.810s 1286.187us 1 1 100.00
hmac_test_hmac256_vectors 8.380s 3054.021us 1 1 100.00
hmac_test_hmac384_vectors 10.790s 519.096us 1 1 100.00
hmac_test_hmac512_vectors 8.990s 1561.576us 1 1 100.00
hmac_stress_all 34.140s 5117.359us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 34.140s 5117.359us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.590s 22.365us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.600s 15.987us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.240s 274.182us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.240s 274.182us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.860s 37.990us 1 1 100.00
hmac_csr_rw 0.730s 26.643us 1 1 100.00
hmac_csr_aliasing 1.950s 227.651us 1 1 100.00
hmac_same_csr_outstanding 1.150s 33.115us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.860s 37.990us 1 1 100.00
hmac_csr_rw 0.730s 26.643us 1 1 100.00
hmac_csr_aliasing 1.950s 227.651us 1 1 100.00
hmac_same_csr_outstanding 1.150s 33.115us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.740s 153.740us 1 1 100.00
hmac_tl_intg_err 2.520s 704.674us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.520s 704.674us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.980s 352.667us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.740s 1553.397us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 72.650s 5977.258us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.760s 24.977us 1 1 100.00