Simulation Results: keymgr

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.87 %
  • code
  • 94.42 %
  • assert
  • 97.49 %
  • func
  • 68.69 %
  • line
  • 98.72 %
  • branch
  • 97.53 %
  • cond
  • 93.40 %
  • toggle
  • 96.41 %
  • FSM
  • 86.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.290s 132.788us 1 1 100.00
random 1 1 100.00
keymgr_random 9.740s 2703.659us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.050s 23.911us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.860s 9.828us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 6.240s 807.347us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 3.180s 346.713us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.040s 32.419us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.860s 9.828us 1 1 100.00
keymgr_csr_aliasing 3.180s 346.713us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 4.020s 126.921us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 2.250s 265.915us 1 1 100.00
keymgr_sideload_kmac 15.360s 882.924us 1 1 100.00
keymgr_sideload_aes 2.250s 71.276us 1 1 100.00
keymgr_sideload_otbn 2.280s 370.374us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.360s 26.815us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 1.490s 59.207us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 3.180s 376.128us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 5.780s 1301.096us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 1.620s 54.113us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.840s 177.300us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 198.310s 15172.348us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.750s 22.824us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.690s 54.834us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.420s 78.012us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.420s 78.012us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.050s 23.911us 1 1 100.00
keymgr_csr_rw 0.860s 9.828us 1 1 100.00
keymgr_csr_aliasing 3.180s 346.713us 1 1 100.00
keymgr_same_csr_outstanding 1.000s 30.498us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.050s 23.911us 1 1 100.00
keymgr_csr_rw 0.860s 9.828us 1 1 100.00
keymgr_csr_aliasing 3.180s 346.713us 1 1 100.00
keymgr_same_csr_outstanding 1.000s 30.498us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 3.810s 294.612us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 3.810s 294.612us 1 1 100.00
keymgr_tl_intg_err 3.650s 1200.768us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.910s 2672.881us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.910s 2672.881us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.910s 2672.881us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.910s 2672.881us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 5.050s 721.314us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 3.810s 294.612us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 3.810s 294.612us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 3.650s 1200.768us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.910s 2672.881us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 4.020s 126.921us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 9.740s 2703.659us 1 1 100.00
keymgr_csr_rw 0.860s 9.828us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 9.740s 2703.659us 1 1 100.00
keymgr_csr_rw 0.860s 9.828us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 9.740s 2703.659us 1 1 100.00
keymgr_csr_rw 0.860s 9.828us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 1.490s 59.207us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.620s 54.113us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.620s 54.113us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 9.740s 2703.659us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 1.790s 153.309us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 3.810s 294.612us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 3.810s 294.612us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 3.810s 294.612us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 4.260s 172.366us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 1.490s 59.207us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 3.810s 294.612us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 3.810s 294.612us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 3.810s 294.612us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 4.260s 172.366us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 4.260s 172.366us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 3.810s 294.612us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 4.260s 172.366us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 3.810s 294.612us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 4.260s 172.366us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 6.110s 489.169us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 54213776695755319845038775021030708934304742193474943865257380725204264173129 528
UVM_INFO @ 489169221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---