Simulation Results: kmac/masked

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.80 %
  • code
  • 69.52 %
  • assert
  • 97.61 %
  • func
  • 78.28 %
  • line
  • 96.35 %
  • branch
  • 90.80 %
  • cond
  • 84.91 %
  • toggle
  • 29.33 %
  • FSM
  • 46.20 %
Validation stages
V1
100.00%
V2
72.41%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 65.550s 21787.241us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.960s 335.926us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.880s 16.142us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 11.980s 1992.113us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 2.690s 92.674us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.330s 44.074us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.880s 16.142us 1 1 100.00
kmac_csr_aliasing 2.690s 92.674us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.680s 16.230us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.260s 82.425us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 3532.010s 426193.334us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 841.820s 62672.933us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 27.310s 5708.594us 1 1 100.00
kmac_test_vectors_sha3_256 24.710s 5817.548us 1 1 100.00
kmac_test_vectors_sha3_384 22.880s 2000.835us 1 1 100.00
kmac_test_vectors_sha3_512 14.060s 4722.809us 1 1 100.00
kmac_test_vectors_shake_128 123.320s 5044.994us 1 1 100.00
kmac_test_vectors_shake_256 1598.590s 25770.172us 1 1 100.00
kmac_test_vectors_kmac 1.860s 66.316us 1 1 100.00
kmac_test_vectors_kmac_xof 1.950s 482.628us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 279.110s 16712.516us 1 1 100.00
app 0 1 0.00
kmac_app 1.040s 72.692us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 3.360s 138.140us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 0.990s 143.791us 0 1 0.00
error 1 1 100.00
kmac_error 43.070s 39452.741us 1 1 100.00
key_error 0 1 0.00
kmac_key_error 1.030s 257.747us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 0.880s 7.064us 0 1 0.00
edn_timeout_error 0 1 0.00
kmac_edn_timeout_error 20.040s 1359.265us 0 1 0.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 0.970s 88.948us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 0.910s 227.941us 0 1 0.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.090s 34.430us 1 1 100.00
stress_all 0 1 0.00
kmac_stress_all 3.350s 755.621us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 0.690s 20.029us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.720s 16.836us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.660s 119.797us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.660s 119.797us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.960s 335.926us 1 1 100.00
kmac_csr_rw 0.880s 16.142us 1 1 100.00
kmac_csr_aliasing 2.690s 92.674us 1 1 100.00
kmac_same_csr_outstanding 1.420s 195.213us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.960s 335.926us 1 1 100.00
kmac_csr_rw 0.880s 16.142us 1 1 100.00
kmac_csr_aliasing 2.690s 92.674us 1 1 100.00
kmac_same_csr_outstanding 1.420s 195.213us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.330s 223.700us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.330s 223.700us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.330s 223.700us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.330s 223.700us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.330s 523.151us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 73.490s 9643.752us 1 1 100.00
kmac_tl_intg_err 2.310s 515.818us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.310s 515.818us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.090s 34.430us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 65.550s 21787.241us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 279.110s 16712.516us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.330s 223.700us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 73.490s 9643.752us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 73.490s 9643.752us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 73.490s 9643.752us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 65.550s 21787.241us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.090s 34.430us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 73.490s 9643.752us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 0.740s 7.226us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 65.550s 21787.241us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 14.860s 3445.780us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 4 test runs
kmac_sideload_invalid 88108952535350664179237740165603328977901574283326836775828464157957969026872 81
UVM_INFO @ 7064149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app 85594897513434705252212032093822558332177453135564674241839995963485250132308 82
UVM_INFO @ 72691916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 5901393474743971643522196058300201536907815082525455260036688605086316395736 83
UVM_INFO @ 138140018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 97981500151982329014998338749819674018500634943055933887385867593384790358078 82
UVM_INFO @ 143790710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 3 test runs
kmac_mubi 42173993997923992700305561209219356105789764556055740167306140597514008030181 82
UVM_INFO @ 7225579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 53003430319153935723351167624843357590041171410255630581014943624291931336683 80
UVM_INFO @ 755620794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 106703772093763854318792048571931828715830675700669272962169971968360317709058 115
UVM_INFO @ 3445780253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 3 test runs
kmac_key_error 114342890305872178420907085969147567746466633132259456822297894518343366533343 83
UVM_ERROR @ 257747093 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 257747093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_edn_timeout_error 18026138380059722955268839493312207910071391226236731980095603074595308258175 95
UVM_ERROR @ 1359265295 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 1359265295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 83635818307735297063530750794384409668811413311093183747745280577440283697859 83
UVM_ERROR @ 227940852 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 227940852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---