Simulation Results: lc_ctrl/volatile_unlock_disabled

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.20 %
  • code
  • 84.64 %
  • assert
  • 94.83 %
  • func
  • 94.13 %
  • line
  • 97.15 %
  • branch
  • 93.70 %
  • cond
  • 79.72 %
  • toggle
  • 88.16 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.540s 44.845us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.830s 28.670us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.810s 61.436us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.530s 55.938us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 36.955us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.330s 32.301us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.810s 61.436us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 36.955us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.740s 118.658us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.320s 232.635us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.040s 34.030us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.450s 39.715us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.650s 312.942us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 10.460s 1707.954us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.650s 312.942us 1 1 100.00
lc_ctrl_prog_failure 1.450s 39.715us 1 1 100.00
lc_ctrl_errors 10.460s 1707.954us 1 1 100.00
lc_ctrl_security_escalation 5.250s 1075.323us 1 1 100.00
lc_ctrl_jtag_state_failure 19.460s 5473.519us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.410s 3324.127us 1 1 100.00
lc_ctrl_jtag_errors 12.320s 2275.586us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.870s 603.709us 1 1 100.00
lc_ctrl_jtag_state_post_trans 15.600s 1656.972us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.410s 3324.127us 1 1 100.00
lc_ctrl_jtag_errors 12.320s 2275.586us 1 1 100.00
lc_ctrl_jtag_access 2.940s 303.574us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 16.980s 16981.620us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.180s 613.578us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.960s 41.429us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.480s 4143.432us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.150s 1119.406us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.180s 29.405us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.270s 183.052us 1 1 100.00
lc_ctrl_jtag_alert_test 1.350s 594.421us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.960s 3258.733us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.740s 40.399us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 55.720s 10368.802us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.940s 78.478us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.280s 370.150us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.280s 370.150us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.830s 28.670us 1 1 100.00
lc_ctrl_csr_rw 0.810s 61.436us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 36.955us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 31.636us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.830s 28.670us 1 1 100.00
lc_ctrl_csr_rw 0.810s 61.436us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 36.955us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 31.636us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.250s 442.824us 1 1 100.00
lc_ctrl_tl_intg_err 1.590s 85.826us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.590s 85.826us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.320s 232.635us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.650s 312.942us 1 1 100.00
lc_ctrl_sec_cm 5.250s 442.824us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.650s 312.942us 1 1 100.00
lc_ctrl_sec_cm 5.250s 442.824us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.650s 312.942us 1 1 100.00
lc_ctrl_sec_cm 5.250s 442.824us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.650s 312.942us 1 1 100.00
lc_ctrl_sec_cm 5.250s 442.824us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.650s 312.942us 1 1 100.00
lc_ctrl_sec_cm 5.250s 442.824us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.650s 312.942us 1 1 100.00
lc_ctrl_sec_cm 5.250s 442.824us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.650s 312.942us 1 1 100.00
lc_ctrl_sec_cm 5.250s 442.824us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.650s 312.942us 1 1 100.00
lc_ctrl_sec_cm 5.250s 442.824us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.250s 1075.323us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.740s 118.658us 1 1 100.00
lc_ctrl_jtag_state_post_trans 15.600s 1656.972us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.490s 7378.042us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.490s 7378.042us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.910s 1494.241us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.740s 477.743us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.740s 477.743us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 31.980s 5495.163us 1 1 100.00