Simulation Results: lc_ctrl/volatile_unlock_enabled

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.19 %
  • code
  • 84.24 %
  • assert
  • 94.69 %
  • func
  • 91.64 %
  • line
  • 97.17 %
  • branch
  • 93.66 %
  • cond
  • 79.41 %
  • toggle
  • 86.46 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.390s 198.162us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.970s 57.244us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.840s 21.784us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.590s 58.254us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.060s 400.678us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.110s 28.990us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.840s 21.784us 1 1 100.00
lc_ctrl_csr_aliasing 1.060s 400.678us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.350s 140.157us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.240s 1076.219us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.740s 37.857us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.910s 46.945us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.660s 970.847us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.970s 679.592us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.660s 970.847us 1 1 100.00
lc_ctrl_prog_failure 1.910s 46.945us 1 1 100.00
lc_ctrl_errors 4.970s 679.592us 1 1 100.00
lc_ctrl_security_escalation 6.590s 605.257us 1 1 100.00
lc_ctrl_jtag_state_failure 43.600s 4738.767us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.610s 669.360us 1 1 100.00
lc_ctrl_jtag_errors 37.210s 15684.207us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.920s 820.431us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.100s 1471.795us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.610s 669.360us 1 1 100.00
lc_ctrl_jtag_errors 37.210s 15684.207us 1 1 100.00
lc_ctrl_jtag_access 1.090s 269.609us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.770s 999.926us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.010s 51.958us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.150s 222.072us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.670s 5978.505us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.230s 355.179us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.180s 46.978us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.180s 240.484us 1 1 100.00
lc_ctrl_jtag_alert_test 1.180s 130.142us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.860s 684.646us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.900s 16.784us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 260.980s 133471.853us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.830s 22.303us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.740s 95.696us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.740s 95.696us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.970s 57.244us 1 1 100.00
lc_ctrl_csr_rw 0.840s 21.784us 1 1 100.00
lc_ctrl_csr_aliasing 1.060s 400.678us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.320s 33.737us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.970s 57.244us 1 1 100.00
lc_ctrl_csr_rw 0.840s 21.784us 1 1 100.00
lc_ctrl_csr_aliasing 1.060s 400.678us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.320s 33.737us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.170s 237.615us 1 1 100.00
lc_ctrl_tl_intg_err 1.790s 258.214us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.790s 258.214us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.240s 1076.219us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.660s 970.847us 1 1 100.00
lc_ctrl_sec_cm 5.170s 237.615us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.660s 970.847us 1 1 100.00
lc_ctrl_sec_cm 5.170s 237.615us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.660s 970.847us 1 1 100.00
lc_ctrl_sec_cm 5.170s 237.615us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.660s 970.847us 1 1 100.00
lc_ctrl_sec_cm 5.170s 237.615us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.660s 970.847us 1 1 100.00
lc_ctrl_sec_cm 5.170s 237.615us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.660s 970.847us 1 1 100.00
lc_ctrl_sec_cm 5.170s 237.615us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.660s 970.847us 1 1 100.00
lc_ctrl_sec_cm 5.170s 237.615us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.660s 970.847us 1 1 100.00
lc_ctrl_sec_cm 5.170s 237.615us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.590s 605.257us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.350s 140.157us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.100s 1471.795us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.770s 1787.180us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.770s 1787.180us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.130s 2936.456us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.820s 346.064us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.820s 346.064us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 23.130s 12126.921us 1 1 100.00