| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
88.00% |
| V3 |
|
0.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| otbn_smoke | 8.000s | 70.450us | 1 | 1 | 100.00 | |
| single_binary | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 73.763us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| otbn_csr_hw_reset | 27.000s | 18.446us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| otbn_csr_rw | 25.000s | 23.114us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| otbn_csr_bit_bash | 30.000s | 164.645us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| otbn_csr_aliasing | 27.000s | 23.492us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| otbn_csr_mem_rw_with_rand_reset | 28.000s | 60.469us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| otbn_csr_rw | 25.000s | 23.114us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 27.000s | 23.492us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| otbn_mem_walk | 72.000s | 3334.969us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| otbn_mem_partial_access | 39.000s | 574.271us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_recovery | 1 | 1 | 100.00 | |||
| otbn_reset | 25.000s | 285.291us | 1 | 1 | 100.00 | |
| multi_error | 1 | 1 | 100.00 | |||
| otbn_multi_err | 57.000s | 164.621us | 1 | 1 | 100.00 | |
| back_to_back | 1 | 1 | 100.00 | |||
| otbn_multi | 169.000s | 1473.701us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| otbn_stress_all | 51.000s | 830.355us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| otbn_escalate | 29.000s | 35.836us | 1 | 1 | 100.00 | |
| zero_state_err_urnd | 1 | 1 | 100.00 | |||
| otbn_zero_state_err_urnd | 5.000s | 60.083us | 1 | 1 | 100.00 | |
| sw_errs_fatal_chk | 1 | 1 | 100.00 | |||
| otbn_sw_errs_fatal_chk | 10.000s | 387.784us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| otbn_alert_test | 32.000s | 17.733us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| otbn_intr_test | 22.000s | 80.354us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 5.000s | 310.629us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 5.000s | 310.629us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 27.000s | 18.446us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 25.000s | 23.114us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 27.000s | 23.492us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 28.402us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 27.000s | 18.446us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 25.000s | 23.114us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 27.000s | 23.492us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 28.402us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mem_integrity | 2 | 2 | 100.00 | |||
| otbn_imem_err | 29.000s | 22.687us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 27.000s | 17.564us | 1 | 1 | 100.00 | |
| internal_integrity | 4 | 4 | 100.00 | |||
| otbn_alu_bignum_mod_err | 29.000s | 69.302us | 1 | 1 | 100.00 | |
| otbn_controller_ispr_rdata_err | 29.000s | 14.297us | 1 | 1 | 100.00 | |
| otbn_mac_bignum_acc_err | 26.000s | 63.110us | 1 | 1 | 100.00 | |
| otbn_urnd_err | 5.000s | 10.381us | 1 | 1 | 100.00 | |
| illegal_bus_access | 1 | 1 | 100.00 | |||
| otbn_illegal_mem_acc | 26.000s | 233.873us | 1 | 1 | 100.00 | |
| otbn_mem_gnt_acc_err | 1 | 1 | 100.00 | |||
| otbn_mem_gnt_acc_err | 25.000s | 20.764us | 1 | 1 | 100.00 | |
| otbn_non_sec_partial_wipe | 1 | 1 | 100.00 | |||
| otbn_partial_wipe | 11.000s | 41.489us | 1 | 1 | 100.00 | |
| tl_intg_err | 1 | 2 | 50.00 | |||
| otbn_sec_cm | 7.000s | 48.977us | 0 | 1 | 0.00 | |
| otbn_tl_intg_err | 12.000s | 66.028us | 1 | 1 | 100.00 | |
| passthru_mem_tl_intg_err | 0 | 1 | 0.00 | |||
| otbn_passthru_mem_tl_intg_err | 6.000s | 137.038us | 0 | 1 | 0.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 7.000s | 48.977us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 7.000s | 48.977us | 0 | 1 | 0.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| otbn_smoke | 8.000s | 70.450us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_dmem_err | 27.000s | 17.564us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_imem_err | 29.000s | 22.687us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| otbn_tl_intg_err | 12.000s | 66.028us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 29.000s | 35.836us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 29.000s | 22.687us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 27.000s | 17.564us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 5.000s | 60.083us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 26.000s | 233.873us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 7.000s | 48.977us | 0 | 1 | 0.00 | |
| sec_cm_controller_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 7.000s | 48.977us | 0 | 1 | 0.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 73.763us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 29.000s | 22.687us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 27.000s | 17.564us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 5.000s | 60.083us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 26.000s | 233.873us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 7.000s | 48.977us | 0 | 1 | 0.00 | |
| sec_cm_scramble_ctrl_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 7.000s | 48.977us | 0 | 1 | 0.00 | |
| sec_cm_start_stop_ctrl_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 29.000s | 35.836us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 29.000s | 22.687us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 27.000s | 17.564us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 5.000s | 60.083us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 26.000s | 233.873us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 7.000s | 48.977us | 0 | 1 | 0.00 | |
| sec_cm_start_stop_ctrl_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 7.000s | 48.977us | 0 | 1 | 0.00 | |
| sec_cm_data_reg_sw_sca | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 73.763us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_redun | 1 | 1 | 100.00 | |||
| otbn_ctrl_redun | 26.000s | 57.786us | 1 | 1 | 100.00 | |
| sec_cm_pc_ctrl_flow_redun | 1 | 1 | 100.00 | |||
| otbn_pc_ctrl_flow_redun | 7.000s | 41.657us | 1 | 1 | 100.00 | |
| sec_cm_rnd_bus_consistency | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 16.000s | 103.511us | 1 | 1 | 100.00 | |
| sec_cm_rnd_rng_digest | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 16.000s | 103.511us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_base_intg_err | 8.000s | 17.814us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_glitch_detect | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 7.000s | 48.977us | 0 | 1 | 0.00 | |
| sec_cm_stack_wr_ptr_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 7.000s | 48.977us | 0 | 1 | 0.00 | |
| sec_cm_rf_bignum_data_reg_sw_integrity | 0 | 1 | 0.00 | |||
| otbn_rf_bignum_intg_err | 0.725s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_rf_bignum_data_reg_sw_glitch_detect | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 7.000s | 48.977us | 0 | 1 | 0.00 | |
| sec_cm_loop_stack_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 7.000s | 48.977us | 0 | 1 | 0.00 | |
| sec_cm_loop_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 9.000s | 30.764us | 1 | 1 | 100.00 | |
| sec_cm_call_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 9.000s | 30.764us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_state_consistency | 1 | 1 | 100.00 | |||
| otbn_sec_wipe_err | 4.000s | 49.247us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 73.763us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 73.763us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 73.763us | 1 | 1 | 100.00 | |
| sec_cm_write_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_multi | 169.000s | 1473.701us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_count | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 73.763us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_sca | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 73.763us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sw_noaccess | 1 | 1 | 100.00 | |||
| otbn_sw_no_acc | 7.000s | 31.115us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 73.763us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 7.000s | 48.977us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| otbn_stress_all_with_rand_reset | 28.000s | 204.643us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| otbn_smoke_vectorized | 7.000s | 90.753us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 1 test run | |||
| otbn_rf_bignum_intg_err | 90581779254900675112373507493481362926048233322834122962645700040377543848359 | None |
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
|
|
| UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 1 test run | |||
| otbn_stress_all_with_rand_reset | 102569603400743650707122775581115113855811510317175201159978335376189115876034 | 160 |
UVM_INFO @ 204642645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. | 1 test run | |||
| otbn_passthru_mem_tl_intg_err | 90134761260219895586802414875000871544117697562056831156906179505732007502864 | 91 |
UVM_INFO @ 137038452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed | 1 test run | |||
| otbn_sec_cm | 115381450678597816938541999162130520594612010228350409581333642514220937417981 | 91 |
UVM_ERROR @ 48977011 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 48977011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|