Simulation Results: pwrmgr

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.58 %
  • code
  • 97.34 %
  • assert
  • 97.39 %
  • func
  • 98.02 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.62 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
86.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.620s 24.844us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.620s 26.006us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.590s 26.185us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.510s 760.434us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.920s 49.215us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.830s 66.920us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.590s 26.185us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 49.215us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.810s 294.297us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.810s 294.297us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.710s 345.338us 1 1 100.00
pwrmgr_lowpower_invalid 0.620s 92.114us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 2.060s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.690s 130.002us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 2.060s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.760s 131.282us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.980s 289.703us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.650s 56.111us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 16.190s 11067.211us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.580s 24.212us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.570s 640.904us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.570s 640.904us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.620s 26.006us 1 1 100.00
pwrmgr_csr_rw 0.590s 26.185us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 49.215us 1 1 100.00
pwrmgr_same_csr_outstanding 0.640s 76.112us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.620s 26.006us 1 1 100.00
pwrmgr_csr_rw 0.590s 26.185us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 49.215us 1 1 100.00
pwrmgr_same_csr_outstanding 0.640s 76.112us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.320s 192.082us 1 1 100.00
pwrmgr_sec_cm 1.190s 720.302us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.190s 720.302us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.190s 720.302us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.320s 192.082us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.930s 791.798us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.760s 131.282us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.540s 1131.544us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.680s 93.050us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.580s 66.682us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.190s 720.302us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.190s 720.302us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.190s 720.302us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.580s 100.807us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.600s 29.812us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.720s 95.860us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.590s 26.185us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.590s 26.185us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.680s 149.678us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 4.470s 1972.190us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 92990996305712816879940541051265887464020199216147299596183814741738469980108 151
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all 38608418358853831555868009582172234619132903848564874217049450416847991921096 1424
UVM_INFO @ 11067211358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---