Simulation Results: rom_ctrl/32kb

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.23 %
  • code
  • 97.01 %
  • assert
  • 97.53 %
  • func
  • 97.14 %
  • line
  • 99.33 %
  • branch
  • 99.27 %
  • cond
  • 98.07 %
  • toggle
  • 95.05 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.520s 1559.306us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.200s 1448.068us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.450s 429.979us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.420s 126.318us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.960s 359.478us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.790s 178.965us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.450s 429.979us 1 1 100.00
rom_ctrl_csr_aliasing 2.960s 359.478us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.890s 169.833us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.210s 127.326us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.140s 166.860us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 18.990s 8341.878us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.360s 306.176us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.430s 556.554us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.930s 561.645us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.930s 561.645us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.200s 1448.068us 1 1 100.00
rom_ctrl_csr_rw 3.450s 429.979us 1 1 100.00
rom_ctrl_csr_aliasing 2.960s 359.478us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.070s 206.228us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.200s 1448.068us 1 1 100.00
rom_ctrl_csr_rw 3.450s 429.979us 1 1 100.00
rom_ctrl_csr_aliasing 2.960s 359.478us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.070s 206.228us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.100s 3029.420us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.080s 564.058us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 195.010s 2203.281us 1 1 100.00
rom_ctrl_tl_intg_err 22.400s 795.444us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 195.010s 2203.281us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 195.010s 2203.281us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.100s 3029.420us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.100s 3029.420us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.100s 3029.420us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.100s 3029.420us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.100s 3029.420us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 195.010s 2203.281us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 195.010s 2203.281us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.520s 1559.306us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.520s 1559.306us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.520s 1559.306us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 22.400s 795.444us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.100s 3029.420us 1 1 100.00
rom_ctrl_kmac_err_chk 7.360s 306.176us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.100s 3029.420us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.100s 3029.420us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.100s 3029.420us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.080s 564.058us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 195.010s 2203.281us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 195.840s 2615.025us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 39166312564826240249929050763844038035013108033290427839717203190415952801508 84
UVM_INFO @ 166860232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---