Simulation Results: rom_ctrl/64kb

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.03 %
  • code
  • 96.90 %
  • assert
  • 96.81 %
  • func
  • 97.37 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 96.88 %
  • toggle
  • 95.57 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.740s 305.342us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.710s 1300.286us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.630s 207.082us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 8.560s 1190.559us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.850s 298.289us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.050s 1042.420us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.630s 207.082us 1 1 100.00
rom_ctrl_csr_aliasing 6.850s 298.289us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.130s 1068.789us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.270s 955.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 7.000s 852.920us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 29.620s 1110.923us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.780s 563.997us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 8.260s 2084.916us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.940s 1063.903us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.940s 1063.903us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.710s 1300.286us 1 1 100.00
rom_ctrl_csr_rw 5.630s 207.082us 1 1 100.00
rom_ctrl_csr_aliasing 6.850s 298.289us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.810s 287.331us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.710s 1300.286us 1 1 100.00
rom_ctrl_csr_rw 5.630s 207.082us 1 1 100.00
rom_ctrl_csr_aliasing 6.850s 298.289us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.810s 287.331us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.840s 6431.224us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 37.390s 6114.876us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 230.760s 1727.155us 1 1 100.00
rom_ctrl_tl_intg_err 95.100s 853.508us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 230.760s 1727.155us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 230.760s 1727.155us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.840s 6431.224us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.840s 6431.224us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.840s 6431.224us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.840s 6431.224us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.840s 6431.224us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 230.760s 1727.155us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 230.760s 1727.155us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.740s 305.342us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.740s 305.342us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.740s 305.342us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 95.100s 853.508us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.840s 6431.224us 1 1 100.00
rom_ctrl_kmac_err_chk 13.780s 563.997us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.840s 6431.224us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.840s 6431.224us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.840s 6431.224us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 37.390s 6114.876us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 230.760s 1727.155us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 108.470s 8954.346us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 67704304918584669431949852792118827429093077574407842909204727448661927406979 84
UVM_INFO @ 852919965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---