Simulation Results: rstmgr

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.89 %
  • code
  • 99.38 %
  • assert
  • 98.53 %
  • func
  • 95.77 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.17 %
  • toggle
  • 98.99 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.320s 292.958us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.740s 107.902us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.710s 66.691us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.470s 380.615us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.060s 106.161us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.800s 121.207us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.710s 66.691us 1 1 100.00
rstmgr_csr_aliasing 1.060s 106.161us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.750s 153.156us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.440s 181.529us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.780s 105.743us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.580s 1553.091us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.580s 1553.091us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.580s 1553.091us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.580s 1553.091us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 13.760s 6538.210us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.740s 98.272us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.460s 155.709us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.460s 155.709us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.740s 107.902us 1 1 100.00
rstmgr_csr_rw 0.710s 66.691us 1 1 100.00
rstmgr_csr_aliasing 1.060s 106.161us 1 1 100.00
rstmgr_same_csr_outstanding 1.000s 162.493us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.740s 107.902us 1 1 100.00
rstmgr_csr_rw 0.710s 66.691us 1 1 100.00
rstmgr_csr_aliasing 1.060s 106.161us 1 1 100.00
rstmgr_same_csr_outstanding 1.000s 162.493us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 10.320s 8433.136us 1 1 100.00
rstmgr_tl_intg_err 2.360s 950.951us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 10.320s 8433.136us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 10.320s 8433.136us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.360s 950.951us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.960s 189.162us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 7.380s 2827.092us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 0.960s 302.414us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 10.320s 8433.136us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.710s 66.691us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.710s 66.691us 1 1 100.00