Simulation Results: spi_device/1r1w

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.94 %
  • code
  • 90.67 %
  • assert
  • 95.40 %
  • func
  • 62.75 %
  • line
  • 98.84 %
  • branch
  • 98.11 %
  • cond
  • 95.83 %
  • toggle
  • 71.19 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 206.310s 35400.796us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.110s 223.310us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.810s 99.756us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 9.840s 1369.733us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 15.310s 13538.565us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.290s 232.308us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.810s 99.756us 1 1 100.00
spi_device_csr_aliasing 15.310s 13538.565us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.640s 74.746us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 0.990s 59.470us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.650s 66.967us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.690s 3.985us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.680s 3.441us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.130s 182.028us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.130s 182.028us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 3.100s 1349.839us 1 1 100.00
spi_device_tpm_sts_read 0.820s 310.967us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 9.290s 2835.169us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 1.640s 81.200us 1 1 100.00
spi_device_flash_all 0.680s 65.503us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 9.040s 25305.549us 1 1 100.00
spi_device_flash_all 0.680s 65.503us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 9.040s 25305.549us 1 1 100.00
spi_device_flash_all 0.680s 65.503us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 0.680s 65.503us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 6.300s 4937.991us 1 1 100.00
spi_device_flash_all 0.680s 65.503us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 6.300s 4937.991us 1 1 100.00
spi_device_flash_all 0.680s 65.503us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 6.300s 4937.991us 1 1 100.00
spi_device_flash_all 0.680s 65.503us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 6.300s 4937.991us 1 1 100.00
spi_device_flash_all 0.680s 65.503us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 6.300s 4937.991us 1 1 100.00
spi_device_flash_all 0.680s 65.503us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 12.550s 4118.921us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 1.770s 249.133us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 1.770s 249.133us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 1.770s 249.133us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 3.240s 374.054us 1 1 100.00
spi_device_read_buffer_direct 4.880s 3173.100us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 1.770s 249.133us 1 1 100.00
spi_device_flash_all 0.680s 65.503us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 0.680s 65.503us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 0.680s 65.503us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.000s 103.743us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.000s 103.743us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 30.760s 35294.582us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 206.310s 35400.796us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 59.320s 8232.886us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 0.890s 222.016us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.660s 20.771us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.640s 14.864us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.610s 125.698us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.610s 125.698us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.110s 223.310us 1 1 100.00
spi_device_csr_rw 1.810s 99.756us 1 1 100.00
spi_device_csr_aliasing 15.310s 13538.565us 1 1 100.00
spi_device_same_csr_outstanding 3.050s 716.220us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.110s 223.310us 1 1 100.00
spi_device_csr_rw 1.810s 99.756us 1 1 100.00
spi_device_csr_aliasing 15.310s 13538.565us 1 1 100.00
spi_device_same_csr_outstanding 3.050s 716.220us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.960s 212.139us 1 1 100.00
spi_device_tl_intg_err 6.490s 745.238us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 6.490s 745.238us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 25322886368383708721516723960688313577855602027250010572900689315386238013671 81
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 2904540 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 2904540 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[927])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 78663004670783761442313213132859675061166468268528638593957309163339095070246 81
UVM_ERROR @ 996514 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf7db0d [111101111101101100001101] vs 0x0 [0])
UVM_ERROR @ 1006514 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb34e2f [101100110100111000101111] vs 0x0 [0])
UVM_ERROR @ 1067514 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf8619c [111110000110000110011100] vs 0x0 [0])
UVM_ERROR @ 1074514 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9dfc9f [100111011111110010011111] vs 0x0 [0])