Simulation Results: sram_ctrl/main

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.07 %
  • code
  • 94.93 %
  • assert
  • 97.69 %
  • func
  • 92.60 %
  • block
  • 95.03 %
  • line
  • 95.65 %
  • branch
  • 92.23 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 353.879us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 17.243us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 44.060us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 33.162us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 63.543us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 351.830us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 44.060us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 63.543us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 105.000s 13424.865us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 36.000s 957.859us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 31.000s 75574.965us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 125.000s 21082.932us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 110.000s 4299.466us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 15.000s 25510.806us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 14.000s 12371.939us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 21.000s 4891.732us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 1574.932us 1 1 100.00
sram_ctrl_partial_access_b2b 93.000s 3921.308us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 3.000s 715.372us 0 1 0.00
sram_ctrl_throughput_w_partial_write 5.000s 2546.395us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 2142.475us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 1639.816us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 350.349us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 227.000s 186312.008us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 56.781us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 220.946us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 220.946us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 17.243us 1 1 100.00
sram_ctrl_csr_rw 1.000s 44.060us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 63.543us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 22.734us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 17.243us 1 1 100.00
sram_ctrl_csr_rw 1.000s 44.060us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 63.543us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 22.734us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 7384.632us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 401.316us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 266.395us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 401.316us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 266.395us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 1639.816us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 1639.816us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 44.060us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 21.000s 4891.732us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 21.000s 4891.732us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 21.000s 4891.732us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 14.000s 12371.939us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 699.072us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 7384.632us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 1388.951us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 353.879us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 353.879us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 21.000s 4891.732us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 401.316us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 14.000s 12371.939us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 401.316us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 401.316us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 353.879us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 401.316us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 14.000s 6410.840us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 71655101271284518231433593829208425744276967440128351486944179842261220786353 86
UVM_INFO @ 715371710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 50698024695026066554167320097178882372760070874487123354216241943836947876260 86
UVM_INFO @ 2546394694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 23362980390437714423096732868359145330792313968025287674438865646023403298224 86
UVM_INFO @ 2142475375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---