Simulation Results: sram_ctrl/ret

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.54 %
  • code
  • 82.10 %
  • assert
  • 97.94 %
  • func
  • 94.57 %
  • block
  • 93.42 %
  • line
  • 94.54 %
  • branch
  • 88.89 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 88.460us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 14.512us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 40.807us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 559.979us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.063us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 112.935us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 40.807us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.063us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 9.000s 5019.590us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 652.147us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 7.000s 766.825us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 112.000s 3143.710us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 1686.736us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 16.000s 2316.398us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 1403.205us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 3.000s 187.135us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 49.909us 1 1 100.00
sram_ctrl_partial_access_b2b 255.000s 126541.342us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 2.000s 27.594us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 26.510us 0 1 0.00
sram_ctrl_throughput_w_readback 1.000s 35.122us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 898.671us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 48.578us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 37.000s 15621.985us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 79.585us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 287.714us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 287.714us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 14.512us 1 1 100.00
sram_ctrl_csr_rw 1.000s 40.807us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.063us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 24.115us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 14.512us 1 1 100.00
sram_ctrl_csr_rw 1.000s 40.807us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.063us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 24.115us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 639.796us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 442.106us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1459.921us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 442.106us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1459.921us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 898.671us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 898.671us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 40.807us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 3.000s 187.135us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 3.000s 187.135us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 3.000s 187.135us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 1403.205us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 101.313us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 639.796us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 140.766us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 88.460us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 88.460us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 3.000s 187.135us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 442.106us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 1403.205us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 442.106us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 442.106us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 88.460us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 442.106us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 13.000s 1083.977us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 100937134566732317474690234137584033950553147256534409965018430676803533764685 86
UVM_INFO @ 27593539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 95109825415729594456751057468049081948719904041766110989153324926463346736463 86
UVM_INFO @ 26510135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 100472887326797703581777308024361893531279396638482846367882584002087374764430 86
UVM_INFO @ 35121803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---