Simulation Results: sysrst_ctrl

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.94 %
  • code
  • 94.00 %
  • assert
  • 95.79 %
  • func
  • 74.02 %
  • line
  • 97.92 %
  • branch
  • 97.85 %
  • cond
  • 96.25 %
  • toggle
  • 99.77 %
  • FSM
  • 78.21 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.450s 2123.793us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.610s 2476.297us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 4.270s 2232.733us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.560s 2331.420us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.110s 6083.433us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.030s 2049.106us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 98.320s 39059.640us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 5.600s 2564.468us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.450s 2079.923us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.030s 2049.106us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.600s 2564.468us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 129.700s 180980.201us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 31.210s 76153.362us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 36.790s 105120.628us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.300s 4935.426us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 2.800s 2521.349us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.300s 2109.739us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 263.600s 176665.238us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.840s 2638.279us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.310s 4083.560us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 71.790s 42539.967us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 177.340s 105038.792us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 0.970s 2080.687us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.470s 2033.024us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.860s 2277.948us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.860s 2277.948us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.110s 6083.433us 1 1 100.00
sysrst_ctrl_csr_rw 2.030s 2049.106us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.600s 2564.468us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.600s 5271.019us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.110s 6083.433us 1 1 100.00
sysrst_ctrl_csr_rw 2.030s 2049.106us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.600s 2564.468us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.600s 5271.019us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 37.370s 22012.395us 1 1 100.00
sysrst_ctrl_tl_intg_err 18.330s 22312.063us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 18.330s 22312.063us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.040s 52354.369us 1 1 100.00