Simulation Results

Simulation Results: uart

09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
81.93 %

code
92.31 %

assert
98.85 %

func
54.62 %

line
99.48 %

branch
97.90 %

cond
97.20 %

toggle
74.67 %

Validation stages

V1		100.00%
V2		90.91%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	1.020s	533.321us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.660s	33.360us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	0.570s	34.941us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	1.130s	48.479us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	0.650s	13.473us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	0.840s	77.956us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	0.570s	34.941us	1	1	100.00
	uart_csr_aliasing	0.650s	13.473us	1	1	100.00

20/22 passed

90.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	2.760s	34867.019us	1	1	100.00
parity				2	2	100.00
	uart_smoke	1.020s	533.321us	1	1	100.00
	uart_tx_rx	2.760s	34867.019us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	25.460s	30816.107us	1	1	100.00
	uart_rx_parity_err	19.920s	279825.606us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	2.760s	34867.019us	1	1	100.00
	uart_intr	25.460s	30816.107us	1	1	100.00
fifo_full				0	1	0.00
	uart_fifo_full	97.410s	76455.137us	0	1	0.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	82.740s	106584.682us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	12.570s	35916.181us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	25.460s	30816.107us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	25.460s	30816.107us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	25.460s	30816.107us	1	1	100.00
perf				1	1	100.00
	uart_perf	16.780s	3893.460us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	1.430s	2947.099us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	1.430s	2947.099us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	87.070s	74956.660us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	22.250s	35340.111us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	5.760s	8184.993us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	10.020s	4536.968us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	147.050s	144464.736us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	1236.020s	329170.529us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	0.630s	11.038us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	0.640s	45.638us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	1.540s	107.488us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	1.540s	107.488us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	0.660s	33.360us	1	1	100.00
	uart_csr_rw	0.570s	34.941us	1	1	100.00
	uart_csr_aliasing	0.650s	13.473us	1	1	100.00
	uart_same_csr_outstanding	0.660s	38.989us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	0.660s	33.360us	1	1	100.00
	uart_csr_rw	0.570s	34.941us	1	1	100.00
	uart_csr_aliasing	0.650s	13.473us	1	1	100.00
	uart_same_csr_outstanding	0.660s	38.989us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	0.760s	319.974us	1	1	100.00
	uart_tl_intg_err	1.050s	88.707us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	1.050s	88.707us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	49.830s	10116.833us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [] vs [*]) Interrupt_pin: TxEmpty				1 test run
	uart_fifo_full	93135830980673538850143525960579911048391617757121095276623923032124387884685	86	UVM_INFO @ 59340676521 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 8/9 UVM_INFO @ 70995456521 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 9/9 UVM_INFO @ 76455136521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: , clk_pulses:				1 test run
	uart_noise_filter	28239491600626982812470493835366894819972685963735086940382058796031835433943	83	UVM_ERROR @ 12144513075 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 12144530024 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (51 [0x33] vs 246 [0xf6]) reg name: uart_reg_block.rdata UVM_ERROR @ 12144563922 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 12144580871 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (51 [0x33] vs 246 [0xf6]) reg name: uart_reg_block.rdata