Simulation Results

Simulation Results: adc_ctrl

13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
65.90 %

code
92.87 %

assert
91.90 %

func
12.92 %

line
98.19 %

branch
96.47 %

cond
86.15 %

toggle
99.76 %

FSM
83.78 %

Validation stages

V1		100.00%
V2		57.89%
V2S		100.00%
V3		0.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	adc_ctrl_smoke	1.530s	5908.973us	1	1	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	1.580s	790.505us	1	1	100.00
csr_rw				1	1	100.00
	adc_ctrl_csr_rw	1.290s	523.954us	1	1	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	39.220s	52436.452us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	1.910s	542.129us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	1.030s	579.195us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	adc_ctrl_csr_rw	1.290s	523.954us	1	1	100.00
	adc_ctrl_csr_aliasing	1.910s	542.129us	1	1	100.00

11/19 passed

57.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	1	0.00
	adc_ctrl_filters_polled	0.670s	432.062us	0	1	0.00
filters_polled_fixed				0	1	0.00
	adc_ctrl_filters_polled_fixed	0.930s	523.977us	0	1	0.00
filters_interrupt				0	1	0.00
	adc_ctrl_filters_interrupt	1.060s	352.817us	0	1	0.00
filters_interrupt_fixed				0	1	0.00
	adc_ctrl_filters_interrupt_fixed	1.200s	457.847us	0	1	0.00
filters_wakeup				0	1	0.00
	adc_ctrl_filters_wakeup	0.770s	376.154us	0	1	0.00
filters_wakeup_fixed				0	1	0.00
	adc_ctrl_filters_wakeup_fixed	0.710s	433.949us	0	1	0.00
filters_both				0	1	0.00
	adc_ctrl_filters_both	1.170s	426.361us	0	1	0.00
clock_gating				0	1	0.00
	adc_ctrl_clock_gating	0.680s	279.733us	0	1	0.00
poweron_counter				1	1	100.00
	adc_ctrl_poweron_counter	3.670s	4394.166us	1	1	100.00
lowpower_counter				1	1	100.00
	adc_ctrl_lowpower_counter	19.100s	32317.470us	1	1	100.00
fsm_reset				1	1	100.00
	adc_ctrl_fsm_reset	36.370s	84920.222us	1	1	100.00
stress_all				1	1	100.00
	adc_ctrl_stress_all	17.830s	49288.482us	1	1	100.00
alert_test				1	1	100.00
	adc_ctrl_alert_test	1.000s	378.580us	1	1	100.00
intr_test				1	1	100.00
	adc_ctrl_intr_test	1.070s	380.511us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	adc_ctrl_tl_errors	1.290s	598.213us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	adc_ctrl_tl_errors	1.290s	598.213us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	adc_ctrl_csr_hw_reset	1.580s	790.505us	1	1	100.00
	adc_ctrl_csr_rw	1.290s	523.954us	1	1	100.00
	adc_ctrl_csr_aliasing	1.910s	542.129us	1	1	100.00
	adc_ctrl_same_csr_outstanding	2.730s	2718.690us	1	1	100.00
tl_d_partial_access				4	4	100.00
	adc_ctrl_csr_hw_reset	1.580s	790.505us	1	1	100.00
	adc_ctrl_csr_rw	1.290s	523.954us	1	1	100.00
	adc_ctrl_csr_aliasing	1.910s	542.129us	1	1	100.00
	adc_ctrl_same_csr_outstanding	2.730s	2718.690us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	adc_ctrl_sec_cm	5.490s	3839.382us	1	1	100.00
	adc_ctrl_tl_intg_err	6.510s	4084.550us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	adc_ctrl_tl_intg_err	6.510s	4084.550us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	adc_ctrl_stress_all_with_rand_reset	4.990s	1983.404us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				9 test runs
	adc_ctrl_filters_polled	36860109142229927569774594010061858401685772285304680540682615326703714151863	386	UVM_INFO @ 432061848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	97753569726318106590536509108625795152782420309128093955698026823385163465419	386	UVM_INFO @ 523977406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	82719962270646223054755010824302086164309844497726170659128940677563743781861	386	UVM_INFO @ 352817407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	44786654934341160954798587998422890064239496901385591431938816128374231148528	386	UVM_INFO @ 457847178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	494233419862474115744237135747857421459310436675067226813809478460682107153	386	UVM_INFO @ 376153669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	106250253148380775602691790894631833521358655618949544671972574697260056569755	386	UVM_INFO @ 433949348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	114498253522863577973163639674122458230059617088578358310427820140808715700903	386	UVM_INFO @ 279733398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	36711021204008927279455492431097325602300894600496726733885411138032649628409	386	UVM_INFO @ 426360926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	3769483577629538502880759096129759017491361777523475002611360730298238707781	440	UVM_INFO @ 1983404467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---