Simulation Results: aes/masked

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.07 %
  • code
  • 94.12 %
  • assert
  • 98.38 %
  • func
  • 71.70 %
  • block
  • 94.25 %
  • line
  • 95.87 %
  • branch
  • 87.07 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 89.590us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 139.731us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 68.423us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 56.936us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 449.484us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 95.350us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 57.835us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 56.936us 1 1 100.00
aes_csr_aliasing 2.000s 95.350us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 139.731us 1 1 100.00
aes_config_error 2.000s 112.139us 1 1 100.00
aes_stress 4.000s 509.000us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 139.731us 1 1 100.00
aes_config_error 2.000s 112.139us 1 1 100.00
aes_stress 4.000s 509.000us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 509.000us 1 1 100.00
aes_b2b 2.000s 68.005us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 509.000us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 139.731us 1 1 100.00
aes_config_error 2.000s 112.139us 1 1 100.00
aes_stress 4.000s 509.000us 1 1 100.00
aes_alert_reset 2.000s 112.311us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 58.566us 1 1 100.00
aes_config_error 2.000s 112.139us 1 1 100.00
aes_alert_reset 2.000s 112.311us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 5.000s 776.809us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 555.179us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 112.311us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 509.000us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 509.000us 1 1 100.00
aes_sideload 4.000s 595.470us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 81.252us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 28.000s 2753.080us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 300.163us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 266.360us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 266.360us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 68.423us 1 1 100.00
aes_csr_rw 2.000s 56.936us 1 1 100.00
aes_csr_aliasing 2.000s 95.350us 1 1 100.00
aes_same_csr_outstanding 1.000s 94.167us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 68.423us 1 1 100.00
aes_csr_rw 2.000s 56.936us 1 1 100.00
aes_csr_aliasing 2.000s 95.350us 1 1 100.00
aes_same_csr_outstanding 1.000s 94.167us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 1.000s 38.638us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 4.000s 106.812us 0 1 0.00
aes_control_fi 2.000s 52.044us 1 1 100.00
aes_cipher_fi 4.000s 65.574us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 91.294us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 91.294us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 91.294us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 91.294us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 113.751us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 1610.895us 1 1 100.00
aes_tl_intg_err 2.000s 279.619us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 279.619us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 112.311us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 91.294us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 91.294us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 139.731us 1 1 100.00
aes_stress 4.000s 509.000us 1 1 100.00
aes_alert_reset 2.000s 112.311us 1 1 100.00
aes_core_fi 2.000s 82.484us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 112.139us 1 1 100.00
aes_stress 4.000s 509.000us 1 1 100.00
aes_core_fi 2.000s 82.484us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 91.294us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 126.993us 1 1 100.00
aes_stress 4.000s 509.000us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 509.000us 1 1 100.00
aes_sideload 4.000s 595.470us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 126.993us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 126.993us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 126.993us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 126.993us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 126.993us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 509.000us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 509.000us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 106.812us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 4.000s 106.812us 0 1 0.00
aes_control_fi 2.000s 52.044us 1 1 100.00
aes_cipher_fi 4.000s 65.574us 1 1 100.00
aes_ctr_fi 3.000s 62.327us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 106.812us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 4.000s 106.812us 0 1 0.00
aes_control_fi 2.000s 52.044us 1 1 100.00
aes_cipher_fi 4.000s 65.574us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 4.000s 65.574us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 106.812us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 106.812us 0 1 0.00
aes_control_fi 2.000s 52.044us 1 1 100.00
aes_ctr_fi 3.000s 62.327us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 106.812us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 4.000s 106.812us 0 1 0.00
aes_control_fi 2.000s 52.044us 1 1 100.00
aes_cipher_fi 4.000s 65.574us 1 1 100.00
aes_ctr_fi 3.000s 62.327us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 112.311us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 4.000s 106.812us 0 1 0.00
aes_control_fi 2.000s 52.044us 1 1 100.00
aes_cipher_fi 4.000s 65.574us 1 1 100.00
aes_ctr_fi 3.000s 62.327us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 4.000s 106.812us 0 1 0.00
aes_control_fi 2.000s 52.044us 1 1 100.00
aes_cipher_fi 4.000s 65.574us 1 1 100.00
aes_ctr_fi 3.000s 62.327us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 106.812us 0 1 0.00
aes_control_fi 2.000s 52.044us 1 1 100.00
aes_ctr_fi 3.000s 62.327us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 106.812us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 4.000s 106.812us 0 1 0.00
aes_control_fi 2.000s 52.044us 1 1 100.00
aes_cipher_fi 4.000s 65.574us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 27.000s 2498.883us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 49284323328367260811891269924872155383589469128945685025895891147285246567861 2300
UVM_INFO @ 38637620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 78952569313002385849200675014165777758806547104744926949070884156591173649883 16893
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_scoreboard.sv:785) scoreboard [scoreboard] # * 1 test run
aes_stress_all 78927171189486271329638572432633878848697807092066782369360166168212431239558 152019
TEST FAILED MESSAGES DID NOT MATCH
0 74 77 77 0
1 00 79 79 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 58342159669768643026129558849283601684933995827415429877606238457237927860265 1043
UVM_INFO @ 2498882747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---