Simulation Results: alert_handler

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.12 %
  • code
  • 90.50 %
  • assert
  • 98.31 %
  • func
  • 81.56 %
  • line
  • 99.66 %
  • branch
  • 97.80 %
  • cond
  • 89.60 %
  • toggle
  • 92.84 %
  • FSM
  • 72.58 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 28.180s 887.505us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.530s 148.197us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.420s 690.776us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 75.580s 1410.528us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 76.400s 2057.989us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.030s 80.048us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.420s 690.776us 1 1 100.00
alert_handler_csr_aliasing 76.400s 2057.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 106.370s 8939.366us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 23.580s 1339.365us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1235.600s 35950.870us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 6.580s 657.704us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 28.180s 887.505us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 25.330s 451.552us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 3.030s 37.271us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 48.800s 7601.016us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 931.400s 81865.326us 1 1 100.00
alert_handler_lpg_stub_clk 1129.060s 77104.315us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2238.920s 126236.375us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 7.080s 765.765us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.010s 19.254us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.230s 10.244us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 4.600s 328.950us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 4.600s 328.950us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.530s 148.197us 1 1 100.00
alert_handler_csr_rw 3.420s 690.776us 1 1 100.00
alert_handler_csr_aliasing 76.400s 2057.989us 1 1 100.00
alert_handler_same_csr_outstanding 13.280s 342.005us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.530s 148.197us 1 1 100.00
alert_handler_csr_rw 3.420s 690.776us 1 1 100.00
alert_handler_csr_aliasing 76.400s 2057.989us 1 1 100.00
alert_handler_same_csr_outstanding 13.280s 342.005us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 49.370s 3004.595us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 49.370s 3004.595us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 49.370s 3004.595us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 49.370s 3004.595us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 168.040s 9219.749us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 8.820s 1185.439us 1 1 100.00
alert_handler_tl_intg_err 14.730s 3209.394us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 14.730s 3209.394us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 49.370s 3004.595us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 28.180s 887.505us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 28.180s 887.505us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 28.180s 887.505us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 28.180s 887.505us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 6.580s 657.704us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 931.400s 81865.326us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 6.580s 657.704us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1235.600s 35950.870us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1235.600s 35950.870us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.820s 1185.439us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.820s 1185.439us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.820s 1185.439us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.820s 1185.439us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 8.820s 1185.439us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.820s 1185.439us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.820s 1185.439us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.820s 1185.439us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 8.820s 1185.439us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 88.240s 1413.752us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 66252048487241332813381867091376307691237312487354013509693004738221052556500 194
UVM_INFO @ 765764525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1199) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
alert_handler_stress_all_with_rand_reset 71260004888098752218140241927336883353324238260040336282786621626303928951214 203
UVM_INFO @ 1413752325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---