Simulation Results: chip

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.57 %
  • code
  • 84.48 %
  • assert
  • 97.37 %
  • func
  • 38.87 %
  • line
  • 94.47 %
  • branch
  • 94.26 %
  • cond
  • 89.25 %
  • toggle
  • 87.26 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
75.09%
V2S
50.00%
V3
61.54%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 145.700s 2676.876us 1 1 100.00
chip_sw_example_rom 64.390s 1960.026us 1 1 100.00
chip_sw_example_manufacturer 161.340s 2550.584us 1 1 100.00
chip_sw_example_concurrency 162.060s 3518.889us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 171.070s 3906.119us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 328.620s 5205.254us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 2936.450s 43756.049us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3732.900s 33439.141us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 44.730s 1893.748us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3732.900s 33439.141us 1 1 100.00
chip_csr_rw 328.620s 5205.254us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.990s 205.474us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 308.090s 4558.878us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 308.090s 4558.878us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 308.090s 4558.878us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 387.070s 4770.588us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 387.070s 4770.588us 1 1 100.00
chip_sw_uart_tx_rx_idx1 402.980s 4335.741us 1 1 100.00
chip_sw_uart_tx_rx_idx2 346.320s 4137.046us 1 1 100.00
chip_sw_uart_tx_rx_idx3 398.600s 4794.784us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1113.310s 8727.899us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1785.920s 13599.819us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 316.710s 4262.811us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 166.170s 4622.232us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 166.170s 4622.232us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 233.400s 4004.232us 1 1 100.00
chip_sw_sleep_pin_wake 0 1 0.00
chip_sw_sleep_pin_wake 151.010s 2866.675us 0 1 0.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 157.090s 3678.393us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 71.950s 2646.266us 1 1 100.00
chip_tap_straps_testunlock0 289.020s 5691.933us 1 1 100.00
chip_tap_straps_rma 121.910s 3119.892us 1 1 100.00
chip_tap_straps_prod 79.400s 2185.477us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 375.160s 5568.878us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 375.160s 5568.878us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 649.780s 8815.152us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1445.560s 13351.110us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 336.060s 4079.970us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 519.520s 5139.621us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3972.700s 18505.087us 1 1 100.00
chip_sw_aes_enc_jitter_en 140.950s 2238.735us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 804.800s 8066.835us 1 1 100.00
chip_sw_hmac_enc_jitter_en 189.860s 3523.212us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1052.630s 8686.216us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 198.090s 2615.100us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 327.430s 5458.553us 1 1 100.00
chip_sw_clkmgr_jitter 137.330s 2766.112us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 187.640s 3184.743us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 466.070s 6927.695us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 223.930s 4654.724us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 157.620s 3186.848us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 223.930s 4654.724us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 164.020s 2952.254us 1 1 100.00
chip_sw_aes_smoketest 168.050s 2982.128us 1 1 100.00
chip_sw_aon_timer_smoketest 205.030s 3328.445us 1 1 100.00
chip_sw_clkmgr_smoketest 125.650s 2735.466us 1 1 100.00
chip_sw_csrng_smoketest 146.600s 2899.775us 1 1 100.00
chip_sw_entropy_src_smoketest 1094.200s 7970.059us 1 1 100.00
chip_sw_gpio_smoketest 200.680s 3131.955us 1 1 100.00
chip_sw_hmac_smoketest 188.990s 3363.237us 1 1 100.00
chip_sw_kmac_smoketest 162.140s 2458.300us 1 1 100.00
chip_sw_otbn_smoketest 1402.170s 10502.587us 1 1 100.00
chip_sw_pwrmgr_smoketest 221.710s 5257.758us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 271.680s 6811.385us 1 1 100.00
chip_sw_rv_plic_smoketest 202.990s 3734.163us 1 1 100.00
chip_sw_rv_timer_smoketest 164.310s 3065.996us 1 1 100.00
chip_sw_rstmgr_smoketest 164.170s 3102.061us 1 1 100.00
chip_sw_sram_ctrl_smoketest 158.190s 2415.944us 1 1 100.00
chip_sw_uart_smoketest 175.880s 3167.785us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 171.720s 3137.621us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 421.690s 5892.564us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7984.390s 60528.952us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3172.380s 17926.949us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 119.181s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 1169.290s 15061.665us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 604.640s 14037.499us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6852.100s 54373.734us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7171.060s 55979.924us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 57.970s 1969.907us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 57.970s 1969.907us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3732.900s 33439.141us 1 1 100.00
chip_same_csr_outstanding 932.380s 12532.818us 1 1 100.00
chip_csr_hw_reset 171.070s 3906.119us 1 1 100.00
chip_csr_rw 328.620s 5205.254us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3732.900s 33439.141us 1 1 100.00
chip_same_csr_outstanding 932.380s 12532.818us 1 1 100.00
chip_csr_hw_reset 171.070s 3906.119us 1 1 100.00
chip_csr_rw 328.620s 5205.254us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 29.720s 939.270us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.660s 33.179us 1 1 100.00
xbar_smoke_large_delays 57.720s 8065.444us 1 1 100.00
xbar_smoke_slow_rsp 44.710s 4609.292us 1 1 100.00
xbar_random_zero_delays 10.510s 128.622us 1 1 100.00
xbar_random_large_delays 197.340s 33536.303us 1 1 100.00
xbar_random_slow_rsp 279.000s 31459.813us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 38.520s 1131.554us 1 1 100.00
xbar_error_and_unmapped_addr 11.900s 95.907us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 53.550s 1805.289us 1 1 100.00
xbar_error_and_unmapped_addr 11.900s 95.907us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 40.950s 1952.176us 1 1 100.00
xbar_access_same_device_slow_rsp 236.500s 29703.381us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 16.060s 182.398us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 71.370s 1228.335us 1 1 100.00
xbar_stress_all_with_error 5.030s 37.926us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 190.440s 665.619us 1 1 100.00
xbar_stress_all_with_reset_error 43.570s 288.397us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3172.380s 17926.949us 1 1 100.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 441.070s 7236.058us 0 1 0.00
rom_e2e_shutdown_exception_c 0 1 0.00
rom_e2e_shutdown_exception_c 496.040s 6392.246us 0 1 0.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 137.341s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 15.554s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 67.559s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 9.571s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 11.600s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 143.918s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 7.612s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 42.546s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 13.981s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 27.963s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 139.729s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 89.081s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 72.252s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 38.056s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 96.448s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 18.550s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 18.920s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 20.840s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 20.160s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 22.000s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 19.140s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 19.220s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 22.110s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 20.860s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 18.490s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 18.910s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 20.510s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 20.460s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 23.640s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 22.530s 10.360us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 177.572s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 70.077s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 65.002s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 65.241s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 62.016s 0.000us 0 1 0.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 5962.860s 28280.993us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 3200.690s 16008.026us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 6150.270s 27949.425us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3333.360s 15773.142us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3489.530s 34481.985us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3489.530s 34481.985us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 162.470s 3038.871us 1 1 100.00
chip_sw_aes_enc_jitter_en 140.950s 2238.735us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 184.800s 2996.933us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 121.440s 2770.722us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 761.580s 7548.380us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 148.830s 2894.262us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 379.220s 4828.007us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 455.490s 4861.977us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 495.090s 4496.182us 1 1 100.00
chip_plic_all_irqs_10 286.820s 3543.082us 1 1 100.00
chip_plic_all_irqs_20 329.060s 3715.547us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 183.180s 3726.498us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1300.910s 15947.959us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 266.270s 4440.472us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 155.190s 2825.707us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.147s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1074.730s 8852.954us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1064.770s 8256.625us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 742.950s 7474.034us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 9401.970s 256213.721us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 227.440s 4264.598us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 221.710s 5257.758us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 227.440s 4264.598us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 437.620s 7499.145us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 437.620s 7499.145us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 276.550s 7389.927us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 300.710s 4540.073us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 619.030s 6156.130us 1 1 100.00
chip_sw_aes_idle 121.440s 2770.722us 1 1 100.00
chip_sw_hmac_enc_idle 215.020s 3325.558us 1 1 100.00
chip_sw_kmac_idle 159.130s 2484.930us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 364.720s 5084.118us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 363.150s 4612.841us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 324.110s 5465.498us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 272.330s 4926.472us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 886.410s 11432.155us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 345.070s 3434.573us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 377.600s 4935.500us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 401.120s 4472.174us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 390.070s 4882.826us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 390.390s 3809.929us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 417.000s 4606.442us 1 1 100.00
chip_sw_ast_clk_outputs 649.780s 8815.152us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 0 1 0.00
chip_sw_clkmgr_external_clk_src_for_lc 949.160s 26570.668us 0 1 0.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 401.120s 4472.174us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 390.070s 4882.826us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 336.060s 4079.970us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 519.520s 5139.621us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3972.700s 18505.087us 1 1 100.00
chip_sw_aes_enc_jitter_en 140.950s 2238.735us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 804.800s 8066.835us 1 1 100.00
chip_sw_hmac_enc_jitter_en 189.860s 3523.212us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1052.630s 8686.216us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 198.090s 2615.100us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 327.430s 5458.553us 1 1 100.00
chip_sw_clkmgr_jitter 137.330s 2766.112us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 151.900s 2567.636us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 405.270s 4690.553us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 646.990s 6924.200us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4303.050s 25849.899us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 150.010s 3202.909us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 166.440s 3362.305us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 723.500s 8116.161us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 199.540s 3788.614us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 390.320s 5448.571us 1 1 100.00
chip_sw_flash_init_reduced_freq 1404.330s 23693.846us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 13401.360s 150813.077us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 649.780s 8815.152us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 355.920s 4850.546us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 241.450s 3360.440us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 455.490s 4861.977us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1074.730s 8852.954us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2070.290s 24866.452us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 313.440s 4274.074us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 416.020s 6305.126us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 215.490s 2726.722us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 4199.800s 23071.279us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 159.690s 3314.443us 1 1 100.00
chip_sw_edn_entropy_reqs 794.360s 7389.959us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 159.690s 3314.443us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2070.290s 24866.452us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 184.560s 3517.791us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1607.710s 24609.395us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 542.460s 5408.701us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 519.520s 5139.621us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 358.050s 3412.762us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 336.060s 4079.970us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3712.620s 44593.880us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1607.710s 24609.395us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 223.980s 3825.456us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1377.320s 11254.477us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 130.020s 2499.444us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3712.620s 44593.880us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 130.020s 2499.444us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 130.020s 2499.444us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 130.020s 2499.444us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 130.020s 2499.444us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 455.490s 4861.977us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 333.580s 11743.706us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 587.820s 5893.005us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 353.310s 5037.548us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 353.310s 5037.548us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 172.010s 2956.980us 1 1 100.00
chip_sw_hmac_enc_jitter_en 189.860s 3523.212us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 215.020s 3325.558us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 923.630s 6867.086us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1697.050s 12026.672us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 426.350s 5136.694us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 396.160s 5313.508us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 399.570s 5395.900us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 287.520s 3956.658us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1377.320s 11254.477us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1052.630s 8686.216us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1352.920s 10518.423us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 761.580s 7548.380us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 5209.260s 20018.674us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 192.160s 3490.429us 1 1 100.00
chip_sw_kmac_mode_kmac 162.520s 2724.211us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 198.090s 2615.100us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1377.320s 11254.477us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 721.790s 11261.459us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 132.670s 3109.229us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 795.420s 6229.589us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 159.130s 2484.930us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 379.220s 4828.007us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 71.950s 2646.266us 1 1 100.00
chip_tap_straps_rma 121.910s 3119.892us 1 1 100.00
chip_tap_straps_prod 79.400s 2185.477us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 156.360s 2542.390us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 721.790s 11261.459us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 721.790s 11261.459us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 721.790s 11261.459us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1073.520s 8749.149us 1 1 100.00
chip_sw_lc_ctrl_broadcast 18 22 81.82
chip_sw_flash_ctrl_lc_rw_en 130.020s 2499.444us 0 1 0.00
chip_sw_flash_rma_unlocked 3712.620s 44593.880us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 198.440s 3168.671us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 591.860s 6022.422us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 463.030s 5584.910us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 523.220s 7875.627us 0 1 0.00
chip_sw_lc_ctrl_transition 721.790s 11261.459us 1 1 100.00
chip_sw_keymgr_key_derivation 1377.320s 11254.477us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 356.660s 8829.149us 1 1 100.00
chip_sw_sram_ctrl_execution_main 621.630s 7667.919us 1 1 100.00
chip_prim_tl_access 333.580s 11743.706us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 949.160s 26570.668us 0 1 0.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 345.070s 3434.573us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 377.600s 4935.500us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 401.120s 4472.174us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 390.070s 4882.826us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 390.390s 3809.929us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 417.000s 4606.442us 1 1 100.00
chip_tap_straps_dev 71.950s 2646.266us 1 1 100.00
chip_tap_straps_rma 121.910s 3119.892us 1 1 100.00
chip_tap_straps_prod 79.400s 2185.477us 1 1 100.00
chip_rv_dm_lc_disabled 48.670s 2025.178us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 153.290s 2875.357us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 73.320s 3009.098us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 90.880s 3465.482us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 179.730s 4086.850us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1549.600s 26648.367us 1 1 100.00
chip_rv_dm_lc_disabled 48.670s 2025.178us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 631.970s 8504.819us 0 1 0.00
chip_sw_lc_walkthrough_prod 691.580s 10755.946us 0 1 0.00
chip_sw_lc_walkthrough_prodend 610.670s 8644.728us 1 1 100.00
chip_sw_lc_walkthrough_rma 389.860s 7101.524us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1549.600s 26648.367us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 1 3 33.33
chip_sw_lc_ctrl_volatile_raw_unlock 996.470s 26233.112us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 53.950s 1924.506us 1 1 100.00
rom_volatile_raw_unlock 54.150s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3986.330s 16983.274us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3972.700s 18505.087us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 619.030s 6156.130us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 619.030s 6156.130us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 619.030s 6156.130us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 282.750s 3505.226us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 721.790s 11261.459us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1607.710s 24609.395us 1 1 100.00
chip_sw_otbn_mem_scramble 282.750s 3505.226us 1 1 100.00
chip_sw_keymgr_key_derivation 1377.320s 11254.477us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 416.460s 4535.229us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 189.110s 3500.099us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1607.710s 24609.395us 1 1 100.00
chip_sw_otbn_mem_scramble 282.750s 3505.226us 1 1 100.00
chip_sw_keymgr_key_derivation 1377.320s 11254.477us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 416.460s 4535.229us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 189.110s 3500.099us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 721.790s 11261.459us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 401.340s 4591.330us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 156.360s 2542.390us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 198.440s 3168.671us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 591.860s 6022.422us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 463.030s 5584.910us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 523.220s 7875.627us 0 1 0.00
chip_sw_lc_ctrl_transition 721.790s 11261.459us 1 1 100.00
chip_prim_tl_access 333.580s 11743.706us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 333.580s 11743.706us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 779.390s 7557.626us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 67.100s 2375.238us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1043.580s 24165.970us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 240.240s 7379.777us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 349.430s 6888.757us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 472.170s 7726.096us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 968.440s 23330.905us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 2 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 804.050s 12974.727us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 437.620s 7499.145us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 955.900s 12694.205us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 410.280s 5559.788us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 67.100s 2375.238us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 242.950s 4334.028us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 507.900s 9724.809us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 214.340s 5787.512us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 134.340s 3294.377us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 477.470s 13245.226us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 648.420s 6923.345us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1173.880s 14343.566us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1937.190s 24704.247us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 154.300s 3013.111us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 455.490s 4861.977us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 356.660s 8829.149us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 356.660s 8829.149us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1173.880s 14343.566us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 477.470s 13245.226us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 410.280s 5559.788us 1 1 100.00
chip_sw_pwrmgr_smoketest 221.710s 5257.758us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 318.500s 5122.916us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 463.230s 6953.406us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 268.610s 5373.190us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1300.910s 15947.959us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 130.970s 2908.185us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 455.490s 4861.977us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1064.770s 8256.625us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 414.480s 4787.601us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 548.470s 5111.497us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 145.040s 2816.456us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 189.110s 3500.099us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 463.230s 6953.406us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 463.230s 6953.406us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 169.890s 2984.081us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1176.860s 17041.783us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1056.620s 14483.616us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 318.500s 5122.916us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 186.430s 3272.736us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 1422.050s 12860.047us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 121.910s 3119.892us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 48.670s 2025.178us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 495.090s 4496.182us 1 1 100.00
chip_plic_all_irqs_10 286.820s 3543.082us 1 1 100.00
chip_plic_all_irqs_20 329.060s 3715.547us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 185.390s 3202.677us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 167.800s 3546.580us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3172.380s 17926.949us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 197.120s 3175.385us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 221.280s 3600.155us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 194.190s 3067.574us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 248.190s 3220.748us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 416.460s 4535.229us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 327.430s 5458.553us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 534.710s 9310.895us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 510.840s 8734.990us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 621.630s 7667.919us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 455.490s 4861.977us 1 1 100.00
chip_sw_data_integrity_escalation 375.160s 5568.878us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 648.420s 6923.345us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1014.840s 21740.067us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 156.890s 2803.783us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 208.020s 3865.607us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 298.890s 4377.365us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1014.840s 21740.067us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1014.840s 21740.067us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2355.030s 20977.482us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2355.030s 20977.482us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 356.160s 7281.133us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3489.530s 34481.985us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 169.040s 2901.955us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 178.770s 3475.079us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 266.510s 4463.257us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 345.470s 3967.533us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 993.970s 8026.725us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5093.650s 31951.581us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1742.890s 12448.840us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 177.800s 3127.802us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 190.510s 2654.910us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 105.210s 2604.203us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9621.070s 68556.234us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1110.550s 6092.769us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 451.250s 5968.146us 0 1 0.00
rom_e2e_jtag_debug_dev 514.530s 7228.694us 0 1 0.00
rom_e2e_jtag_debug_rma 456.600s 6306.570us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 58.450s 2627.870us 0 1 0.00
rom_e2e_jtag_inject_dev 213.590s 5317.976us 0 1 0.00
rom_e2e_jtag_inject_rma 72.030s 2675.134us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 72.703s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 230.340s 3591.860us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 374.220s 3091.544us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 631.070s 5061.526us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1045.410s 8206.823us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 211.260s 2390.091us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 579.520s 5602.935us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 63.520s 2064.114us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 184.840s 3728.969us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 0 1 0.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 346.480s 6423.816us 0 1 0.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 333.690s 5853.451us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1173.880s 14343.566us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 451.250s 5968.146us 0 1 0.00
rom_e2e_jtag_debug_dev 514.530s 7228.694us 0 1 0.00
rom_e2e_jtag_debug_rma 456.600s 6306.570us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 434.510s 6191.414us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 455.490s 4861.977us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5381.800s 38710.056us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5381.800s 38710.056us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 179.530s 3393.123us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 387.070s 4770.588us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3207.500s 19796.190us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 214.710s 3804.819us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 19.980s 10.360us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 5.720s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 155.290s 3442.538us 1 1 100.00
chip_sw_otp_ctrl_descrambling 154.160s 3579.409us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 272.400s 4716.533us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 11.409s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 170.660s 3365.495us 1 1 100.00
ate_bootstrap_flash_erase 582.770s 10010.160us 0 1 0.00
ate_bootstrap_one_frame 6063.910s 43900.216us 1 1 100.00
ate_bootstrap_disjoint 9397.160s 78657.434us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 81251155447509715822199878858555423804325240700379989964774188841640470881845 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 5260282705657402778756124265194263237022975707379608098286783459679151475288 None
Another command (pid=483380) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=498158) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=500342) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 102462723963964197284975572243657233272989516092720465532799462318708680769902 None
Another command (pid=610487) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=591862) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=625514) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 69005135020258463568746572532606544967872196010506171687407954673321797053843 None
Another command (pid=738040) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=677081) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=743982) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 20737121374133927840936668918038207785523433245954464867132512216746978082938 None
---- STDERR ----
Another command (pid=606515) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=499470) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 55392680313562338508159902531061745984053815493962135010298457401384029694442 None
Another command (pid=622693) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=536844) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=625514) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 84512800945446401820684634240989049239160777362771421660312642800451489313130 None
Another command (pid=484923) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=384953) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=601223) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 48579241673324343174526560100709555072234096293257922157869731491699542942432 None
---- STDERR ----
Another command (pid=596071) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 31879220283176201970575882448642416502674226690236166824164471935481410443970 None
Another command (pid=651732) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=676592) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=669589) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 83132666706290088860587667424233211057146905570170504793503406040120454240054 None
Another command (pid=500954) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=618508) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=435148) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 69385214403646167606048892905224208836948810476362969786297623853867092802199 None
Another command (pid=501719) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=638107) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=400154) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 19530891726676472054402690539592344872561199184513852227434452619362539047150 None
Another command (pid=498158) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=500342) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=445405) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 107579929921496997381981095978983656732513795916068794914218176869896878884487 None
Another command (pid=631516) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=621008) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=665061) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 5064301063504451354992782204239118435579338983722895847340742644117156463317 None
Another command (pid=630587) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=501719) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=638107) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 41269514784029845744154875416739280190612780129147024132336592574110518846364 None
Another command (pid=602648) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=596071) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=606515) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 12936873042744265390321326386685881171886381133629466759642063796985657516590 None
---- STDERR ----
Another command (pid=703558) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=811067) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 19073206824862780904086492999969141730597780572151096780768315063985930124202 None
Another command (pid=657713) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=665061) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=652658) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 34432267504217605076377026631264104849566420322624305903124323532488825416194 None
Another command (pid=498781) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=500342) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=445405) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 50301998771889749247594397497660800923662204619381820828610900860821038242052 None
Another command (pid=405061) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=445405) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=430713) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 98127278335337100124833048842482509810501936394167133512140255744142972233282 None
Another command (pid=513357) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=564708) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=442202) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 75800634673332373955239147241579476862118116181266370679889898165715103781675 None
---- STDERR ----
Another command (pid=500342) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=445405) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 21636825044832743286489178727812981339377101311590445379919030701917618926577 None
Another command (pid=403226) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=470803) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=408800) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 52956606621879014823440257043898785509381803576725218570542225926739631275301 None
Another command (pid=498158) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=500342) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=445405) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 13989821839084095639286959915285480280361637142039965295882412136608543614316 None
Another command (pid=439206) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=403226) is running. Waiting for it to complete on the server (server_pid=282461)...
Another command (pid=470803) is running. Waiting for it to complete on the server (server_pid=282461)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 7 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 36428900624492703969943696170537544600538916077045289529583139539622886456118 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 61894831647893696267558076930512636675365416609695960741589537181568414062441 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 83263234552831513632672800138942117002120874129471160722850182038959796590462 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 74812845470833044097577404792578064160331203556990536285118456597784662852627 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 86567274376239004002859174999897719846019941672297550912460937766616875767707 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 65275279991050633994204167781026639494098879013978377151265596708504811904064 310
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 64301854798079458402139771167656198921566506338953276112440259290086245215128 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 113919427117072816445946069789779279048704133273943894271309783960382718697209 368
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 98670767728885560078909212387169103576439473199215353514712639092056854690637 367
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 97337379747527952414531397878802824819243410559248732470521462557166782799494 367
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 108562304669923230593384915866832766770440034806411054505172806438977233189610 328
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 43286960050550345505469417622629008162872257403281041720596994685034897289972 327
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 2354296244672335068227545471122419453332302605879643890675999012963928580065 328
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 84502040803122083289875932997248456223198269570274648763572717283147023094087 369
UVM_INFO @ 8504.819080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 106775665369495590125284764717615392210710093236245797045628162182276560845154 369
UVM_INFO @ 10755.946428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 45859371091945782278728840746321468433559586524339212843315812153515222254166 341
UVM_INFO @ 7101.523825 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 3 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 90659681726451613467215046575790446619193110239965028997933202723591016944309 344
UVM_ERROR @ 13245.226000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 13245.226000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 63790406860309358857120867294987248764545334835519168078377683799143883827962 325
UVM_ERROR @ 6888.757000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6888.757000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 5957841987870883641522842808152457188559306433880264616675165142804855476370 319
UVM_ERROR @ 7499.144500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7499.144500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 46691798050567919211180642361167342654396404744203554761225956368334606182959 327
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 32063110322263322816475578156121331290061176810806608463000827871083310469956 326
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 18195428907159403265624408555325589178925868534242142136897854235387778335678 327
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 2 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 78265030383239192457307072599085498645576563456795639308410344419204396318902 313
UVM_ERROR @ 3294.376780 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3294.376780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 70015089656678649948341685445295103124218885645548343349104148367094672712055 342
UVM_ERROR @ 9724.809008 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 9724.809008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 19161502218733221634087356664643003352437199487069520633511932824132464735318 362
UVM_INFO @ 12026.671579 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 28234542218677207537626782047656025223517622338716479256042907107908155303764 336
UVM_INFO @ 20018.673580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 31987077786750221822110303785745162432952160682039910195479492809422696087284 217
TL item was: req: (cip_tl_seq_item@31088) { a_addr: 'h107c4 a_data: 'h1162f6c1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h23 a_opcode: 'h4 a_user: 'h18d38 d_param: 'h0 d_source: 'h23 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1969.907220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 8700555719857482303714370937816526525422176396271116865566819349744154390254 224
TL item was: req: (cip_tl_seq_item@30490) { a_addr: 'h1057c a_data: 'hec2ae20f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h4 a_user: 'h19e5b d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1893.748072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 15856322019246910656853824726129188192501912092070858795453044446948776476303 362
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 25095845546502909045381771236890775665675648683081745516977755472011861584304 325
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 96705986380734030772446986571606301460438132317889267206704371891395152615207 368
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 46930095549473411566369905578777827042591883432998921372377895848339962770025 328
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 102062759800546480032352073925276407192548996654488625279808594566397388543575 301
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(pin_wkup_req_o))' 1 test run
chip_sw_sleep_pin_wake 66057328835663906312103870903932776980354558422962915355627193770367844012937 318
UVM_ERROR @ 2866.675500 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A
UVM_INFO @ 2866.675500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 107647996350564147999494273350259102406983456200347234376021871699728259152947 327
UVM_INFO @ 3600.155434 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 9373116839112642478361739200854857107389273082926097021488670208237656547723 309
UVM_INFO @ 2499.443840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 85169523305156749488917923523362550928264396720981559888463176151762232226871 342
UVM_INFO @ 7875.627400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 20090829253581038149973186748266795637076049367013831466523253446509116828684 316
UVM_ERROR @ 3728.969230 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3728.969230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 83184692331674205483624915748965401397161446044006456673461674896041960408740 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] max attempt reached to get lc status LcTokenError! 1 test run
chip_sw_lc_ctrl_volatile_raw_unlock 31603879613711503911974769428951291168118024498627400252044323037480244867405 308
UVM_INFO @ 26233.112073 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 1570891902300483167769782341898815110454366666840611705858345799706005751279 303
UVM_ERROR @ 2375.238186 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2375.238186 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 92126409876817937991203491392061663320368146602566178379059601809139412494397 332
UVM_INFO @ 34481.985337 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:372)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 69217612304386557105309153855709163465272246956603476759236676019611870189387 307
UVM_INFO @ 2894.261753 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 3546623705564796873264630148395428660495140220742382091977041644018411550105 308
UVM_INFO @ 2825.707211 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 54392814008789499018704881416822701606642374314507766174546387340535016925564 None
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_clkmgr_external_clk_src_for_lc 55914258188919583244294240123648253524107485749075598140852886129089685003462 306
UVM_INFO @ 26570.667532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 102218083500299241683567556048385180639839775040692893664522323095452818315566 343
UVM_INFO @ 3591.859611 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: * 1 test run
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 20636049084080240121127053217646065904712417827800173470852571820575204375390 316
UVM_INFO @ 6423.816316 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. 1 test run
chip_sw_rv_dm_access_after_wakeup 79887568418556240257945997713208425609854648074287458923704516131308277387511 329
UVM_INFO @ 12860.046616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 100427014204400787311359479002529661244259820281266914081634744007673812478658 215
UVM_INFO @ 2025.177895 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. 1 test run
chip_sw_rv_core_ibex_lockstep_glitch 94998958301572116196000421476403177236074922809601049551107300293696458378200 331
UVM_INFO @ 2604.202968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_idle_load 29008594422074682560706883109663858111756534968426298093920883871389657081789 318
UVM_INFO @ 15061.664747 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_sleep_load 90112814148235147060813356715326159035980102906468832914217632783753913514227 337
UVM_INFO @ 14037.499482 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 24123398555229814657340223767450465466389989843907486741572722796740569165513 327
UVM_INFO @ 13351.109852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 38754191409573666675174739551905119589096444523898458363367313785666972059652 272
UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_exception_c 10317436650232944618614982423934666555728021443773465579302787036998629525352 319
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 6392.245535 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_output 90976075269771284605689059174077515656750949652752999806345872241317032162246 312
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 7236.057993 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 26505907003366807762931451982288872100469007884077918436278404790485644712607 325
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 97499073488004811527906670618748867116755483751867391522354346015634257811445 328
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_no_meas 60314684083650346729439095949284868024015008491949517778610624772601967721940 319
UVM_INFO @ 16008.025538 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 92798207756855238227214078653237140313721311476888769368898281299701106627589 327
UVM_ERROR @ 5892.564480 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5892.564480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---