Simulation Results: clkmgr

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.21 %
  • code
  • 96.91 %
  • assert
  • 93.36 %
  • func
  • 83.36 %
  • line
  • 98.02 %
  • branch
  • 97.75 %
  • cond
  • 88.76 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.240s 153.356us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.780s 50.067us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.860s 20.330us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.390s 1108.103us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.660s 164.576us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.220s 62.791us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.860s 20.330us 1 1 100.00
clkmgr_csr_aliasing 1.660s 164.576us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.760s 80.799us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.770s 35.345us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.770s 39.888us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.770s 59.208us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.240s 153.356us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 3.090s 977.754us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 1.680s 467.384us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 3.090s 977.754us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 0.880s 42.407us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.720s 22.701us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.430s 131.671us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.430s 131.671us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.780s 50.067us 1 1 100.00
clkmgr_csr_rw 0.860s 20.330us 1 1 100.00
clkmgr_csr_aliasing 1.660s 164.576us 1 1 100.00
clkmgr_same_csr_outstanding 0.910s 69.920us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.780s 50.067us 1 1 100.00
clkmgr_csr_rw 0.860s 20.330us 1 1 100.00
clkmgr_csr_aliasing 1.660s 164.576us 1 1 100.00
clkmgr_same_csr_outstanding 0.910s 69.920us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
clkmgr_sec_cm 1.500s 155.610us 1 1 100.00
clkmgr_tl_intg_err 2.060s 141.790us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 656.440s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 656.440s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 656.440s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 656.440s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 832.420s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.060s 141.790us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 3.090s 977.754us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 1.680s 467.384us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 656.440s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.850s 109.345us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.770s 55.607us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.740s 55.945us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.950s 32.808us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.810s 17.073us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.860s 20.330us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 1.500s 155.610us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.860s 20.330us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.860s 20.330us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 1.500s 155.610us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.240s 647.905us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 8.090s 803.110us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
clkmgr_shadow_reg_errors 33871004753181933422319131687664491729883566094430157362272906464863355692799 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 70317767704970838241434056067027774389665298734809156449841893311361003883431 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---