Simulation Results: csrng

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.03 %
  • code
  • 92.10 %
  • assert
  • 94.54 %
  • func
  • 68.46 %
  • block
  • 96.99 %
  • line
  • 97.62 %
  • branch
  • 92.51 %
  • toggle
  • 92.56 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 36.901us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 34.647us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 37.003us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 7.000s 160.967us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 5.000s 276.706us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 78.761us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 37.003us 1 1 100.00
csrng_csr_aliasing 5.000s 276.706us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 285.225us 1 1 100.00
alerts 1 1 100.00
csrng_alert 9.000s 388.078us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 42.322us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 2.000s 27.948us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 2.000s 27.948us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 169.000s 7677.427us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 13.895us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 82.678us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 8.000s 245.194us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 8.000s 245.194us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 34.647us 1 1 100.00
csrng_csr_rw 2.000s 37.003us 1 1 100.00
csrng_csr_aliasing 5.000s 276.706us 1 1 100.00
csrng_same_csr_outstanding 2.000s 18.593us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 34.647us 1 1 100.00
csrng_csr_rw 2.000s 37.003us 1 1 100.00
csrng_csr_aliasing 5.000s 276.706us 1 1 100.00
csrng_same_csr_outstanding 2.000s 18.593us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 5.000s 480.906us 1 1 100.00
csrng_tl_intg_err 4.000s 90.768us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 1.000s 6.035us 0 1 0.00
csrng_csr_rw 2.000s 37.003us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 9.000s 388.078us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 169.000s 7677.427us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 285.225us 1 1 100.00
csrng_err 2.000s 42.322us 1 1 100.00
csrng_sec_cm 5.000s 480.906us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 285.225us 1 1 100.00
csrng_err 2.000s 42.322us 1 1 100.00
csrng_sec_cm 5.000s 480.906us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 285.225us 1 1 100.00
csrng_err 2.000s 42.322us 1 1 100.00
csrng_sec_cm 5.000s 480.906us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 285.225us 1 1 100.00
csrng_err 2.000s 42.322us 1 1 100.00
csrng_sec_cm 5.000s 480.906us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 285.225us 1 1 100.00
csrng_err 2.000s 42.322us 1 1 100.00
csrng_sec_cm 5.000s 480.906us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 9.000s 388.078us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 285.225us 1 1 100.00
csrng_err 2.000s 42.322us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 169.000s 7677.427us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 9.000s 388.078us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 90.768us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 285.225us 1 1 100.00
csrng_err 2.000s 42.322us 1 1 100.00
csrng_sec_cm 5.000s 480.906us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 285.225us 1 1 100.00
csrng_err 2.000s 42.322us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 285.225us 1 1 100.00
csrng_err 2.000s 42.322us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 285.225us 1 1 100.00
csrng_err 2.000s 42.322us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 285.225us 1 1 100.00
csrng_err 2.000s 42.322us 1 1 100.00
csrng_sec_cm 5.000s 480.906us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 285.225us 1 1 100.00
csrng_err 2.000s 42.322us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 43.000s 2654.959us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 76786146104114027973093516372979535193637357265536670888545462482445279045355 100
UVM_INFO @ 27948276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 29692156527644023562104908205780640174969916277194302767980427321564899194371 99
UVM_INFO @ 6035097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all_with_rand_reset 94657070813230821642776635333928300835622703493899784851531223463797583657780 138
UVM_INFO @ 2654958911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---