Simulation Results: edn/edn0

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.99 %
  • code
  • 80.80 %
  • assert
  • 95.01 %
  • func
  • 79.17 %
  • line
  • 97.17 %
  • branch
  • 90.24 %
  • cond
  • 86.42 %
  • toggle
  • 81.79 %
  • FSM
  • 48.39 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.830s 53.839us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.920s 12.663us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.870s 11.823us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.910s 466.777us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.170s 43.179us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.060s 218.919us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.870s 11.823us 1 1 100.00
edn_csr_aliasing 1.170s 43.179us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.990s 46.991us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.990s 46.991us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.990s 46.991us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.890s 19.730us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.230s 25.785us 1 1 100.00
errs 1 1 100.00
edn_err 0.960s 64.666us 1 1 100.00
disable 1 2 50.00
edn_disable 0.870s 14.166us 1 1 100.00
edn_disable_auto_req_mode 1.560s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 2.570s 587.703us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.840s 26.271us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.010s 127.425us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.630s 209.712us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.630s 209.712us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.920s 12.663us 1 1 100.00
edn_csr_rw 0.870s 11.823us 1 1 100.00
edn_csr_aliasing 1.170s 43.179us 1 1 100.00
edn_same_csr_outstanding 0.960s 27.415us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.920s 12.663us 1 1 100.00
edn_csr_rw 0.870s 11.823us 1 1 100.00
edn_csr_aliasing 1.170s 43.179us 1 1 100.00
edn_same_csr_outstanding 0.960s 27.415us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.870s 580.004us 1 1 100.00
edn_tl_intg_err 1.830s 183.133us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.880s 32.777us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.230s 25.785us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.870s 580.004us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.870s 580.004us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.870s 580.004us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.870s 580.004us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.230s 25.785us 1 1 100.00
edn_sec_cm 6.870s 580.004us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.230s 25.785us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.830s 183.133us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 71.280s 22783.503us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 100129288046359669135931120058212906261505141312971400027090417822953754102597 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---