Simulation Results: edn/edn1

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.30 %
  • code
  • 82.21 %
  • assert
  • 97.14 %
  • func
  • 82.56 %
  • line
  • 98.18 %
  • branch
  • 93.07 %
  • cond
  • 89.85 %
  • toggle
  • 86.78 %
  • FSM
  • 43.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.860s 19.462us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.770s 52.733us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.740s 18.288us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.440s 147.613us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.040s 21.028us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.340s 141.774us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.740s 18.288us 1 1 100.00
edn_csr_aliasing 1.040s 21.028us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.300s 53.007us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.300s 53.007us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.300s 53.007us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.890s 19.905us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.990s 53.024us 1 1 100.00
errs 1 1 100.00
edn_err 0.980s 21.431us 1 1 100.00
disable 2 2 100.00
edn_disable 0.730s 12.315us 1 1 100.00
edn_disable_auto_req_mode 0.960s 46.289us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.030s 208.340us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.860s 17.618us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.780s 28.634us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.870s 73.132us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.870s 73.132us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.770s 52.733us 1 1 100.00
edn_csr_rw 0.740s 18.288us 1 1 100.00
edn_csr_aliasing 1.040s 21.028us 1 1 100.00
edn_same_csr_outstanding 1.080s 37.991us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.770s 52.733us 1 1 100.00
edn_csr_rw 0.740s 18.288us 1 1 100.00
edn_csr_aliasing 1.040s 21.028us 1 1 100.00
edn_same_csr_outstanding 1.080s 37.991us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.580s 441.491us 1 1 100.00
edn_tl_intg_err 1.800s 1581.217us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.040s 21.038us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.990s 53.024us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.580s 441.491us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.580s 441.491us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.580s 441.491us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.580s 441.491us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.990s 53.024us 1 1 100.00
edn_sec_cm 2.580s 441.491us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.990s 53.024us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.800s 1581.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 84.650s 17093.526us 1 1 100.00