Simulation Results: flash_ctrl

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.67 %
  • code
  • 94.32 %
  • assert
  • 96.94 %
  • func
  • 95.76 %
  • line
  • 95.96 %
  • branch
  • 97.21 %
  • cond
  • 94.03 %
  • toggle
  • 98.01 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 53.330s 44.796us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 13.160s 28.501us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 22.520s 27.571us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.760s 59.796us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 33.380s 7077.484us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 18.940s 993.359us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.880s 221.441us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.760s 59.796us 1 1 100.00
flash_ctrl_csr_aliasing 18.940s 993.359us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 7.470s 30.065us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.890s 32.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 16.790s 24.116us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 16.480s 188.325us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1462.500s 623336.330us 1 1 100.00
flash_ctrl_hw_rma_reset 663.130s 320294.378us 1 1 100.00
flash_ctrl_lcmgr_intg 5.920s 41.556us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1028.880s 334367.711us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 145.610s 1464.143us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 47.360s 2286.676us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2571.240s 216734.962us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 45.700s 380.300us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 18.160s 85.284us 1 1 100.00
flash_ctrl_rw_evict_all_en 17.500s 67.438us 1 1 100.00
flash_ctrl_re_evict 17.450s 150.246us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 25.110s 48.824us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 25.110s 48.824us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 169.070s 23171.542us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 15.860s 1529.279us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 484.170s 452.503us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 498.100s 23116.716us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 274.300s 2343.010us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 969.180s 2298.722us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.550s 25.141us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 99.890s 5825.111us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 12.070s 34.328us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.800s 23.384us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 431.220s 959.722us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 75.120s 16916.901us 1 1 100.00
flash_ctrl_otp_reset 61.030s 40.334us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1462.500s 623336.330us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 96.130s 4771.199us 1 1 100.00
flash_ctrl_intr_wr 42.120s 2340.295us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 82.730s 70781.261us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 133.410s 55791.125us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 40.980s 2105.248us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 36.170s 709.599us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 13.760s 106.369us 1 1 100.00
flash_ctrl_ro_derr 113.440s 2947.669us 1 1 100.00
flash_ctrl_rw_derr 196.010s 2806.615us 1 1 100.00
flash_ctrl_derr_detect 94.500s 807.362us 1 1 100.00
flash_ctrl_integrity 324.400s 19983.996us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 12.350s 231.992us 1 1 100.00
flash_ctrl_ro_serr 94.640s 924.143us 1 1 100.00
flash_ctrl_rw_serr 113.200s 23707.879us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 60.700s 1314.877us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 39.150s 1267.500us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 130.710s 7001.623us 1 1 100.00
flash_ctrl_write_word_sweep 7.120s 44.105us 1 1 100.00
flash_ctrl_read_word_sweep 7.230s 111.452us 1 1 100.00
flash_ctrl_ro 92.990s 1575.469us 1 1 100.00
flash_ctrl_rw 392.590s 39585.399us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 21.320s 777.284us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 567.900s 252262.403us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 33.920s 10034.235us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.720s 86.278us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.980s 74.719us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 14.000s 61.971us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 14.000s 61.971us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 22.520s 27.571us 1 1 100.00
flash_ctrl_csr_rw 8.760s 59.796us 1 1 100.00
flash_ctrl_csr_aliasing 18.940s 993.359us 1 1 100.00
flash_ctrl_same_csr_outstanding 14.560s 534.794us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 22.520s 27.571us 1 1 100.00
flash_ctrl_csr_rw 8.760s 59.796us 1 1 100.00
flash_ctrl_csr_aliasing 18.940s 993.359us 1 1 100.00
flash_ctrl_same_csr_outstanding 14.560s 534.794us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 27.590s 245.224us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 27.590s 245.224us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 27.590s 245.224us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 27.590s 245.224us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 40.730s 206.422us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1786.360s 1542.270us 1 1 100.00
flash_ctrl_tl_intg_err 298.970s 656.864us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 298.970s 656.864us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 298.970s 656.864us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.160s 247.207us 1 1 100.00
flash_ctrl_wr_intg 7.040s 94.052us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 53.330s 44.796us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 61.030s 40.334us 1 1 100.00
flash_ctrl_disable 12.070s 34.328us 1 1 100.00
flash_ctrl_sec_info_access 34.480s 552.317us 1 1 100.00
flash_ctrl_connect 7.800s 23.384us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.940s 80.882us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.760s 59.796us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 27.590s 245.224us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.760s 59.796us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 27.590s 245.224us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.760s 59.796us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 27.590s 245.224us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 12.070s 34.328us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.160s 247.207us 1 1 100.00
flash_ctrl_access_after_disable 6.120s 78.478us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 14.720s 40.658us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 12.070s 34.328us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 15.860s 1529.279us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 392.590s 39585.399us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 113.200s 23707.879us 1 1 100.00
flash_ctrl_rw_derr 196.010s 2806.615us 1 1 100.00
flash_ctrl_integrity 324.400s 19983.996us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1462.500s 623336.330us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1786.360s 1542.270us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1786.360s 1542.270us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1786.360s 1542.270us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1786.360s 1542.270us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 9.100s 787.887us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 10.770s 23.425us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 7.910s 35.999us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1786.360s 1542.270us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1786.360s 1542.270us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1786.360s 1542.270us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 27.640s 1182.154us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 102.400s 616.344us 1 1 100.00