Simulation Results: hmac

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.16 %
  • code
  • 97.76 %
  • assert
  • 97.16 %
  • func
  • 42.57 %
  • line
  • 99.69 %
  • branch
  • 99.01 %
  • cond
  • 95.96 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.580s 1262.770us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.720s 61.008us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.070s 25.027us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 14.280s 4020.245us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.240s 2000.731us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 78.210s 16621.875us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.070s 25.027us 1 1 100.00
hmac_csr_aliasing 6.240s 2000.731us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 7.640s 1664.782us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 40.580s 1137.910us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 180.000s 7841.835us 1 1 100.00
hmac_test_sha384_vectors 462.610s 20423.740us 1 1 100.00
hmac_test_sha512_vectors 21.330s 3606.323us 1 1 100.00
hmac_test_hmac256_vectors 7.990s 1110.862us 1 1 100.00
hmac_test_hmac384_vectors 7.900s 259.444us 1 1 100.00
hmac_test_hmac512_vectors 9.470s 1211.171us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 19.210s 958.475us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 169.130s 10894.471us 1 1 100.00
error 1 1 100.00
hmac_error 53.270s 5728.981us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 29.010s 7591.862us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.580s 1262.770us 1 1 100.00
hmac_long_msg 7.640s 1664.782us 1 1 100.00
hmac_back_pressure 40.580s 1137.910us 1 1 100.00
hmac_datapath_stress 169.130s 10894.471us 1 1 100.00
hmac_burst_wr 19.210s 958.475us 1 1 100.00
hmac_stress_all 3047.510s 100065.239us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.580s 1262.770us 1 1 100.00
hmac_long_msg 7.640s 1664.782us 1 1 100.00
hmac_back_pressure 40.580s 1137.910us 1 1 100.00
hmac_datapath_stress 169.130s 10894.471us 1 1 100.00
hmac_wipe_secret 29.010s 7591.862us 1 1 100.00
hmac_test_sha256_vectors 180.000s 7841.835us 1 1 100.00
hmac_test_sha384_vectors 462.610s 20423.740us 1 1 100.00
hmac_test_sha512_vectors 21.330s 3606.323us 1 1 100.00
hmac_test_hmac256_vectors 7.990s 1110.862us 1 1 100.00
hmac_test_hmac384_vectors 7.900s 259.444us 1 1 100.00
hmac_test_hmac512_vectors 9.470s 1211.171us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.580s 1262.770us 1 1 100.00
hmac_long_msg 7.640s 1664.782us 1 1 100.00
hmac_back_pressure 40.580s 1137.910us 1 1 100.00
hmac_datapath_stress 169.130s 10894.471us 1 1 100.00
hmac_burst_wr 19.210s 958.475us 1 1 100.00
hmac_error 53.270s 5728.981us 1 1 100.00
hmac_wipe_secret 29.010s 7591.862us 1 1 100.00
hmac_test_sha256_vectors 180.000s 7841.835us 1 1 100.00
hmac_test_sha384_vectors 462.610s 20423.740us 1 1 100.00
hmac_test_sha512_vectors 21.330s 3606.323us 1 1 100.00
hmac_test_hmac256_vectors 7.990s 1110.862us 1 1 100.00
hmac_test_hmac384_vectors 7.900s 259.444us 1 1 100.00
hmac_test_hmac512_vectors 9.470s 1211.171us 1 1 100.00
hmac_stress_all 3047.510s 100065.239us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 3047.510s 100065.239us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.680s 34.540us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.660s 14.702us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.210s 234.605us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.210s 234.605us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.720s 61.008us 1 1 100.00
hmac_csr_rw 1.070s 25.027us 1 1 100.00
hmac_csr_aliasing 6.240s 2000.731us 1 1 100.00
hmac_same_csr_outstanding 1.920s 251.948us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.720s 61.008us 1 1 100.00
hmac_csr_rw 1.070s 25.027us 1 1 100.00
hmac_csr_aliasing 6.240s 2000.731us 1 1 100.00
hmac_same_csr_outstanding 1.920s 251.948us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.040s 135.403us 1 1 100.00
hmac_tl_intg_err 1.970s 379.432us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.970s 379.432us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.580s 1262.770us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.570s 431.934us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 30.210s 10699.987us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.500s 72.891us 1 1 100.00