Simulation Results: i2c

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.43 %
  • code
  • 77.85 %
  • assert
  • 97.25 %
  • func
  • 81.18 %
  • line
  • 96.32 %
  • branch
  • 92.12 %
  • cond
  • 85.01 %
  • toggle
  • 72.95 %
  • FSM
  • 42.86 %
Validation stages
V1
100.00%
V2
85.37%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 30.780s 2686.547us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 20.730s 4528.159us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.790s 22.908us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.840s 40.351us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.620s 168.075us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.250s 202.424us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.880s 73.159us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.840s 40.351us 1 1 100.00
i2c_csr_aliasing 1.250s 202.424us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.490s 44.396us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 8.850s 1028.386us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 27.710s 1378.120us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 1.050s 25.441us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 129.870s 16414.133us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 43.270s 16950.268us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.380s 244.383us 1 1 100.00
i2c_host_fifo_fmt_empty 4.420s 405.278us 1 1 100.00
i2c_host_fifo_reset_rx 3.000s 213.322us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 46.360s 6652.915us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 14.130s 4257.762us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 1.120s 60.275us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.920s 2484.406us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 93.110s 72769.380us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 2.650s 1911.188us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 31.120s 3995.783us 1 1 100.00
i2c_target_intr_smoke 2.660s 1229.610us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.150s 160.278us 1 1 100.00
i2c_target_fifo_reset_tx 1.250s 255.892us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 40.750s 44949.896us 1 1 100.00
i2c_target_stress_rd 31.120s 3995.783us 1 1 100.00
i2c_target_intr_stress_wr 22.510s 19895.240us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.290s 4551.259us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 1.120s 863.118us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 2.580s 1468.308us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 6.170s 11190.383us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.790s 559.953us 1 1 100.00
i2c_target_fifo_watermarks_tx 0.870s 83.228us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 27.710s 1378.120us 1 1 100.00
i2c_host_perf_precise 2.140s 83.670us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 14.130s 4257.762us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 4.730s 462.446us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 2.270s 2289.536us 1 1 100.00
i2c_target_nack_acqfull_addr 2.560s 1058.495us 1 1 100.00
i2c_target_nack_txstretch 1.120s 1475.330us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 4.520s 2745.483us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.540s 493.805us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.710s 26.720us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.740s 17.686us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.700s 223.500us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.700s 223.500us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.790s 22.908us 1 1 100.00
i2c_csr_rw 0.840s 40.351us 1 1 100.00
i2c_csr_aliasing 1.250s 202.424us 1 1 100.00
i2c_same_csr_outstanding 0.970s 64.965us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.790s 22.908us 1 1 100.00
i2c_csr_rw 0.840s 40.351us 1 1 100.00
i2c_csr_aliasing 1.250s 202.424us 1 1 100.00
i2c_same_csr_outstanding 0.970s 64.965us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 2.070s 144.380us 1 1 100.00
i2c_sec_cm 1.180s 337.379us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 2.070s 144.380us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 11.240s 1370.056us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.980s 57.995us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 2.440s 892.766us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 3 test runs
i2c_host_error_intr 2470215754710796408102349605767342337815159461049388976141049438590148907378 88
UVM_INFO @ 44395845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 42469681266502621495334588169417083877564951762598332425523911638516096057568 109
UVM_INFO @ 1028385818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 112340654609251496872679494196905284489742424319217036631354400357223201426203 86
UVM_INFO @ 892765853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 4138489553626134608546168221049276140821359683568341572134268838473740801057 84
UVM_INFO @ 2484406447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 51893741203399090468267709371663712331970285743803031249035858926698925256450 78
UVM_INFO @ 57995197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! 1 test run
i2c_target_hrst 108642318305892477211620192805162503243307717367114632220286810961313538554109 79
UVM_INFO @ 11190383158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 90777297425226517707518651234096417457361021179206515161290866204999603566809 85
UVM_INFO @ 1370055917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead 1 test run
i2c_host_mode_toggle 49788060041595429491976257922683743116079531500977372319077534601266172462587 87
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * 1 test run
i2c_target_nack_txstretch 112962364861781024071298982858516240681639702202248212178931539993541090286143 78
UVM_INFO @ 1475329950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---