Simulation Results: keymgr

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.52 %
  • code
  • 94.72 %
  • assert
  • 97.49 %
  • func
  • 55.35 %
  • line
  • 98.72 %
  • branch
  • 97.53 %
  • cond
  • 93.20 %
  • toggle
  • 95.77 %
  • FSM
  • 88.37 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.060s 89.553us 1 1 100.00
random 1 1 100.00
keymgr_random 3.510s 141.013us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.120s 13.243us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.390s 29.030us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 7.040s 804.963us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 2.850s 71.138us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.370s 49.477us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.390s 29.030us 1 1 100.00
keymgr_csr_aliasing 2.850s 71.138us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 3.640s 73.402us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 4.320s 511.205us 1 1 100.00
keymgr_sideload_kmac 4.390s 1027.746us 1 1 100.00
keymgr_sideload_aes 2.700s 72.276us 1 1 100.00
keymgr_sideload_otbn 2.290s 80.245us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.330s 46.409us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.880s 280.066us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.330s 76.314us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 3.170s 261.130us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 3.130s 335.201us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 2.920s 228.242us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 14.320s 2310.403us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.940s 49.848us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.730s 55.443us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.280s 41.345us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.280s 41.345us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.120s 13.243us 1 1 100.00
keymgr_csr_rw 1.390s 29.030us 1 1 100.00
keymgr_csr_aliasing 2.850s 71.138us 1 1 100.00
keymgr_same_csr_outstanding 2.140s 70.730us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.120s 13.243us 1 1 100.00
keymgr_csr_rw 1.390s 29.030us 1 1 100.00
keymgr_csr_aliasing 2.850s 71.138us 1 1 100.00
keymgr_same_csr_outstanding 2.140s 70.730us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 7.610s 2303.448us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 7.610s 2303.448us 1 1 100.00
keymgr_tl_intg_err 3.690s 149.303us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.420s 469.095us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.420s 469.095us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.420s 469.095us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.420s 469.095us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 2.900s 484.194us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 7.610s 2303.448us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 7.610s 2303.448us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 3.690s 149.303us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.420s 469.095us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 3.640s 73.402us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 3.510s 141.013us 1 1 100.00
keymgr_csr_rw 1.390s 29.030us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 3.510s 141.013us 1 1 100.00
keymgr_csr_rw 1.390s 29.030us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 3.510s 141.013us 1 1 100.00
keymgr_csr_rw 1.390s 29.030us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.880s 280.066us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.130s 335.201us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.130s 335.201us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 3.510s 141.013us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.620s 327.041us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.610s 2303.448us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.610s 2303.448us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 7.610s 2303.448us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 3.580s 256.580us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.880s 280.066us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 7.610s 2303.448us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.610s 2303.448us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 7.610s 2303.448us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.580s 256.580us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.580s 256.580us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 7.610s 2303.448us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.580s 256.580us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.610s 2303.448us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 3.580s 256.580us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 3.510s 116.986us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 34669476140902804722211609264153593941117924072775715080417370132526961951501 322
UVM_INFO @ 116986106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---