Simulation Results: lc_ctrl/volatile_unlock_disabled

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.98 %
  • code
  • 84.29 %
  • assert
  • 94.69 %
  • func
  • 93.95 %
  • line
  • 97.20 %
  • branch
  • 93.85 %
  • cond
  • 79.43 %
  • toggle
  • 87.40 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.110s 54.827us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.130s 37.024us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 18.308us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.620s 206.473us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.530s 144.125us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.190s 22.658us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 18.308us 1 1 100.00
lc_ctrl_csr_aliasing 1.530s 144.125us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.380s 59.246us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.160s 394.425us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.770s 37.877us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.550s 34.516us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.370s 3904.846us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 10.080s 4444.962us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.370s 3904.846us 1 1 100.00
lc_ctrl_prog_failure 1.550s 34.516us 1 1 100.00
lc_ctrl_errors 10.080s 4444.962us 1 1 100.00
lc_ctrl_security_escalation 5.710s 777.142us 1 1 100.00
lc_ctrl_jtag_state_failure 18.870s 2850.215us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.210s 385.257us 1 1 100.00
lc_ctrl_jtag_errors 16.900s 3653.801us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.780s 470.916us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.290s 1088.416us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.210s 385.257us 1 1 100.00
lc_ctrl_jtag_errors 16.900s 3653.801us 1 1 100.00
lc_ctrl_jtag_access 8.100s 1972.990us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 28.930s 1356.303us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.060s 66.850us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.110s 218.666us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.790s 2695.910us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.880s 319.724us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.020s 109.616us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.510s 536.861us 1 1 100.00
lc_ctrl_jtag_alert_test 1.240s 129.689us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 12.360s 1458.332us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.920s 19.133us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 62.540s 5456.264us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.020s 35.081us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.890s 135.885us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.890s 135.885us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.130s 37.024us 1 1 100.00
lc_ctrl_csr_rw 1.000s 18.308us 1 1 100.00
lc_ctrl_csr_aliasing 1.530s 144.125us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.400s 31.707us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.130s 37.024us 1 1 100.00
lc_ctrl_csr_rw 1.000s 18.308us 1 1 100.00
lc_ctrl_csr_aliasing 1.530s 144.125us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.400s 31.707us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.740s 272.582us 1 1 100.00
lc_ctrl_tl_intg_err 1.720s 91.711us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.720s 91.711us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.160s 394.425us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.370s 3904.846us 1 1 100.00
lc_ctrl_sec_cm 6.740s 272.582us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.370s 3904.846us 1 1 100.00
lc_ctrl_sec_cm 6.740s 272.582us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.370s 3904.846us 1 1 100.00
lc_ctrl_sec_cm 6.740s 272.582us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.370s 3904.846us 1 1 100.00
lc_ctrl_sec_cm 6.740s 272.582us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.370s 3904.846us 1 1 100.00
lc_ctrl_sec_cm 6.740s 272.582us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.370s 3904.846us 1 1 100.00
lc_ctrl_sec_cm 6.740s 272.582us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.370s 3904.846us 1 1 100.00
lc_ctrl_sec_cm 6.740s 272.582us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.370s 3904.846us 1 1 100.00
lc_ctrl_sec_cm 6.740s 272.582us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.710s 777.142us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.380s 59.246us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.290s 1088.416us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.030s 1014.381us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.030s 1014.381us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.510s 5508.756us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.070s 832.764us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.070s 832.764us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 82.510s 3736.159us 1 1 100.00