Simulation Results: lc_ctrl/volatile_unlock_enabled

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.60 %
  • code
  • 83.38 %
  • assert
  • 94.83 %
  • func
  • 93.59 %
  • line
  • 97.04 %
  • branch
  • 93.08 %
  • cond
  • 78.92 %
  • toggle
  • 84.29 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.170s 52.451us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.840s 71.115us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.820s 21.230us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.060s 192.538us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 94.501us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.320s 29.972us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.820s 21.230us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 94.501us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.380s 74.440us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.560s 622.914us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.750s 22.355us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.830s 53.738us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.750s 1506.122us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.350s 364.319us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.750s 1506.122us 1 1 100.00
lc_ctrl_prog_failure 1.830s 53.738us 1 1 100.00
lc_ctrl_errors 7.350s 364.319us 1 1 100.00
lc_ctrl_security_escalation 4.950s 799.382us 1 1 100.00
lc_ctrl_jtag_state_failure 65.290s 13733.665us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.050s 292.053us 1 1 100.00
lc_ctrl_jtag_errors 36.850s 4194.213us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.210s 1021.331us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.190s 365.351us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.050s 292.053us 1 1 100.00
lc_ctrl_jtag_errors 36.850s 4194.213us 1 1 100.00
lc_ctrl_jtag_access 2.800s 94.319us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 16.270s 4810.255us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.390s 107.245us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.980s 486.941us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.090s 6946.766us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.270s 4968.540us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.330s 24.390us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.020s 183.290us 1 1 100.00
lc_ctrl_jtag_alert_test 1.680s 63.925us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.630s 1130.182us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.960s 26.568us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 21.290s 7983.274us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.900s 19.323us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.140s 147.568us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.140s 147.568us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.840s 71.115us 1 1 100.00
lc_ctrl_csr_rw 0.820s 21.230us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 94.501us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.230s 20.236us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.840s 71.115us 1 1 100.00
lc_ctrl_csr_rw 0.820s 21.230us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 94.501us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.230s 20.236us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.140s 885.977us 1 1 100.00
lc_ctrl_tl_intg_err 1.490s 68.103us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.490s 68.103us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.560s 622.914us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.750s 1506.122us 1 1 100.00
lc_ctrl_sec_cm 6.140s 885.977us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.750s 1506.122us 1 1 100.00
lc_ctrl_sec_cm 6.140s 885.977us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.750s 1506.122us 1 1 100.00
lc_ctrl_sec_cm 6.140s 885.977us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.750s 1506.122us 1 1 100.00
lc_ctrl_sec_cm 6.140s 885.977us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.750s 1506.122us 1 1 100.00
lc_ctrl_sec_cm 6.140s 885.977us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.750s 1506.122us 1 1 100.00
lc_ctrl_sec_cm 6.140s 885.977us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.750s 1506.122us 1 1 100.00
lc_ctrl_sec_cm 6.140s 885.977us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.750s 1506.122us 1 1 100.00
lc_ctrl_sec_cm 6.140s 885.977us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.950s 799.382us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.380s 74.440us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.190s 365.351us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.100s 665.782us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.100s 665.782us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.420s 4151.222us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.230s 422.569us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.230s 422.569us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 15.100s 855.102us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 96104571528598798702346285582102670195837158265721301010958567235105941441506 732
UVM_INFO @ 855102014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---