Simulation Results: otbn

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.14 %
  • code
  • 85.35 %
  • assert
  • 87.58 %
  • func
  • 94.49 %
  • block
  • 99.23 %
  • line
  • 99.42 %
  • branch
  • 94.45 %
  • toggle
  • 84.16 %
  • FSM
  • 63.38 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 167.513us 1 1 100.00
single_binary 1 1 100.00
otbn_single 33.000s 125.652us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 36.000s 69.344us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 35.000s 16.025us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 37.000s 31.975us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 36.000s 21.490us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 37.000s 113.671us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 35.000s 16.025us 1 1 100.00
otbn_csr_aliasing 36.000s 21.490us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 120.000s 5698.666us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 53.000s 1134.970us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 26.000s 309.997us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 50.000s 184.673us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 23.000s 65.654us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 11.000s 103.400us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 35.000s 12.442us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 7.000s 10.641us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 9.000s 27.337us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 36.000s 32.190us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 32.000s 40.244us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 7.000s 409.408us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 7.000s 409.408us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 36.000s 69.344us 1 1 100.00
otbn_csr_rw 35.000s 16.025us 1 1 100.00
otbn_csr_aliasing 36.000s 21.490us 1 1 100.00
otbn_same_csr_outstanding 4.000s 61.728us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 36.000s 69.344us 1 1 100.00
otbn_csr_rw 35.000s 16.025us 1 1 100.00
otbn_csr_aliasing 36.000s 21.490us 1 1 100.00
otbn_same_csr_outstanding 4.000s 61.728us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 36.000s 20.211us 1 1 100.00
otbn_dmem_err 39.000s 29.540us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 40.000s 220.699us 1 1 100.00
otbn_controller_ispr_rdata_err 39.000s 188.862us 1 1 100.00
otbn_mac_bignum_acc_err 33.000s 72.880us 1 1 100.00
otbn_urnd_err 9.000s 21.138us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 35.000s 20.189us 1 1 100.00
otbn_mem_gnt_acc_err 0 1 0.00
otbn_mem_gnt_acc_err 60.000s 10005.110us 0 1 0.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 137.711us 1 1 100.00
tl_intg_err 1 2 50.00
otbn_sec_cm 23.000s 99.218us 0 1 0.00
otbn_tl_intg_err 19.000s 489.419us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 42.000s 192.299us 1 1 100.00
prim_fsm_check 0 1 0.00
otbn_sec_cm 23.000s 99.218us 0 1 0.00
prim_count_check 0 1 0.00
otbn_sec_cm 23.000s 99.218us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 167.513us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 39.000s 29.540us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 36.000s 20.211us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 19.000s 489.419us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 35.000s 12.442us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 36.000s 20.211us 1 1 100.00
otbn_dmem_err 39.000s 29.540us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 10.641us 1 1 100.00
otbn_illegal_mem_acc 35.000s 20.189us 1 1 100.00
otbn_sec_cm 23.000s 99.218us 0 1 0.00
sec_cm_controller_fsm_sparse 0 1 0.00
otbn_sec_cm 23.000s 99.218us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 33.000s 125.652us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 36.000s 20.211us 1 1 100.00
otbn_dmem_err 39.000s 29.540us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 10.641us 1 1 100.00
otbn_illegal_mem_acc 35.000s 20.189us 1 1 100.00
otbn_sec_cm 23.000s 99.218us 0 1 0.00
sec_cm_scramble_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 23.000s 99.218us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 35.000s 12.442us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 36.000s 20.211us 1 1 100.00
otbn_dmem_err 39.000s 29.540us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 10.641us 1 1 100.00
otbn_illegal_mem_acc 35.000s 20.189us 1 1 100.00
otbn_sec_cm 23.000s 99.218us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 23.000s 99.218us 0 1 0.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 33.000s 125.652us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 38.000s 13.135us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 14.045us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 81.000s 336.068us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 81.000s 336.068us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 67.912us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 23.000s 99.218us 0 1 0.00
sec_cm_stack_wr_ptr_ctr_redun 0 1 0.00
otbn_sec_cm 23.000s 99.218us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 7.000s 189.928us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 23.000s 99.218us 0 1 0.00
sec_cm_loop_stack_ctr_redun 0 1 0.00
otbn_sec_cm 23.000s 99.218us 0 1 0.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 15.000s 125.030us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 15.000s 125.030us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 17.000s 59.212us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 33.000s 125.652us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 33.000s 125.652us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 33.000s 125.652us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 23.000s 65.654us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 33.000s 125.652us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 33.000s 125.652us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 7.000s 35.553us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 33.000s 125.652us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
otbn_sec_cm 23.000s 99.218us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 30.000s 177.542us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 91.658us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 62606957361438134038152045138915614255233459327206458937004873213854586352607 170
UVM_INFO @ 177542206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_mem_gnt_acc_err_vseq.sv:41) [otbn_mem_gnt_acc_err_vseq] timeout occurred! 1 test run
otbn_mem_gnt_acc_err 968013107680160937201328704547964636428783187576272532669125054067337432344 108
UVM_INFO @ 10005110133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed 1 test run
otbn_sec_cm 34409068294133906869569502748190897857203690512335933625515768810457890916136 121
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 99218345 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed
UVM_ERROR @ 99218345 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 99218345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---