Simulation Results: otp_ctrl

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.36 %
  • code
  • 75.60 %
  • assert
  • 94.57 %
  • func
  • 67.90 %
  • line
  • 88.47 %
  • branch
  • 83.07 %
  • cond
  • 89.74 %
  • toggle
  • 70.89 %
  • FSM
  • 45.83 %
Validation stages
V1
100.00%
V2
90.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.750s 835.285us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 2.520s 138.056us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.320s 252.577us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.580s 114.518us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.700s 605.488us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.500s 153.186us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.020s 1613.127us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.580s 114.518us 1 1 100.00
otp_ctrl_csr_aliasing 3.500s 153.186us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.400s 96.728us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.140s 39.583us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 14.180s 1827.230us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.470s 293.961us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 10.160s 2687.067us 1 1 100.00
otp_ctrl_check_fail 16.040s 2289.976us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 2.670s 159.197us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 9.540s 837.613us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 2.720s 146.549us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 4.630s 198.867us 1 1 100.00
otp_ctrl_parallel_lc_esc 6.490s 269.358us 1 1 100.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 3.140s 313.328us 0 1 0.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 11.320s 3268.964us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 4.180s 3133.105us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 23.360s 8538.305us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.630s 160.218us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.630s 195.801us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.690s 196.825us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.690s 196.825us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.320s 252.577us 1 1 100.00
otp_ctrl_csr_rw 1.580s 114.518us 1 1 100.00
otp_ctrl_csr_aliasing 3.500s 153.186us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.780s 279.033us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.320s 252.577us 1 1 100.00
otp_ctrl_csr_rw 1.580s 114.518us 1 1 100.00
otp_ctrl_csr_aliasing 3.500s 153.186us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.780s 279.033us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
otp_ctrl_tl_intg_err 8.100s 2502.579us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 8.100s 2502.579us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 2.520s 138.056us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 2.520s 138.056us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.490s 269.358us 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.490s 269.358us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.490s 269.358us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.490s 269.358us 1 1 100.00
otp_ctrl_macro_errs 11.320s 3268.964us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.490s 269.358us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.490s 269.358us 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.490s 269.358us 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.490s 269.358us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.490s 269.358us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.490s 269.358us 1 1 100.00
otp_ctrl_macro_errs 11.320s 3268.964us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.490s 269.358us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.490s 269.358us 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.470s 293.961us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 16.040s 2289.976us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 9.540s 837.613us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 9.540s 837.613us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 9.540s 837.613us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 9.540s 837.613us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 9.540s 837.613us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 2.520s 138.056us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 9.540s 837.613us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 2.520s 138.056us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.710s 10937.288us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 2.670s 159.197us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 2.520s 138.056us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 2.520s 138.056us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 11.320s 3268.964us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 10.780s 3574.058us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 21.110s 1106.917us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 2 test runs
otp_ctrl_dai_errs 41048570216812390609484776655108396262414688834385732390836311999693979431367 2035
UVM_INFO @ 313328234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 49802034799231805926931149517949788425536174047750267635989493717825042198085 13549
UVM_INFO @ 2289975585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 88053396751554004499199079955708174156196780278809097836473571736697133272942 6716
UVM_INFO @ 1106917030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---