Simulation Results: pwrmgr

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.31 %
  • code
  • 95.63 %
  • assert
  • 98.43 %
  • func
  • 97.86 %
  • line
  • 99.09 %
  • branch
  • 96.18 %
  • cond
  • 95.90 %
  • toggle
  • 90.96 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.610s 31.493us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.650s 28.297us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.580s 17.704us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.480s 331.831us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.880s 32.211us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.730s 131.649us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.580s 17.704us 1 1 100.00
pwrmgr_csr_aliasing 0.880s 32.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.630s 188.075us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.630s 188.075us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.760s 39.172us 1 1 100.00
pwrmgr_lowpower_invalid 0.590s 79.739us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.840s 72.847us 1 1 100.00
pwrmgr_reset_invalid 0.830s 114.496us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.840s 72.847us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.910s 352.839us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.800s 479.329us 1 1 100.00
disable_rom_integrity_check 0 1 0.00
pwrmgr_disable_rom_integrity_check 0.910s 1000.000us 0 1 0.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.110s 595.695us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.640s 18.130us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.700s 243.079us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.700s 243.079us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.650s 28.297us 1 1 100.00
pwrmgr_csr_rw 0.580s 17.704us 1 1 100.00
pwrmgr_csr_aliasing 0.880s 32.211us 1 1 100.00
pwrmgr_same_csr_outstanding 0.700s 27.112us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.650s 28.297us 1 1 100.00
pwrmgr_csr_rw 0.580s 17.704us 1 1 100.00
pwrmgr_csr_aliasing 0.880s 32.211us 1 1 100.00
pwrmgr_same_csr_outstanding 0.700s 27.112us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.970s 115.379us 1 1 100.00
pwrmgr_sec_cm 1.210s 707.875us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.210s 707.875us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.210s 707.875us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.970s 115.379us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.420s 1030.253us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.910s 352.839us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.590s 1284.199us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.800s 71.545us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.590s 32.012us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.210s 707.875us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.210s 707.875us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.210s 707.875us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.650s 34.152us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.590s 42.887us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.780s 277.576us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.580s 17.704us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.580s 17.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.680s 626.886us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 2.570s 10007.981us 0 1 0.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 40677406723124436314728076056212808555802388763398906724192293984651323825459 79
UVM_ERROR @ 626886181 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 626886181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_disable_rom_integrity_check 99995896861866473433677027308960239939812432419444914577375939826570025304071 82
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [pwrmgr_common_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all_with_rand_reset 48214395832764340693705302947683097344481628140834872398578991273616219854908 78
UVM_INFO @ 10007981112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---