Simulation Results: rom_ctrl/32kb

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.76 %
  • code
  • 96.82 %
  • assert
  • 96.81 %
  • func
  • 96.66 %
  • line
  • 99.33 %
  • branch
  • 99.27 %
  • cond
  • 97.47 %
  • toggle
  • 94.71 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.880s 182.210us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.570s 756.107us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.400s 129.809us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.720s 170.331us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.970s 477.216us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.580s 140.287us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.400s 129.809us 1 1 100.00
rom_ctrl_csr_aliasing 2.970s 477.216us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.370s 1169.978us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.200s 160.482us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.750s 254.766us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.400s 864.943us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.510s 306.761us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.570s 126.136us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.170s 555.416us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.170s 555.416us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.570s 756.107us 1 1 100.00
rom_ctrl_csr_rw 4.400s 129.809us 1 1 100.00
rom_ctrl_csr_aliasing 2.970s 477.216us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.670s 679.630us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.570s 756.107us 1 1 100.00
rom_ctrl_csr_rw 4.400s 129.809us 1 1 100.00
rom_ctrl_csr_aliasing 2.970s 477.216us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.670s 679.630us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.300s 4614.470us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.190s 858.834us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 105.410s 1457.218us 1 1 100.00
rom_ctrl_tl_intg_err 24.590s 463.899us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 105.410s 1457.218us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 105.410s 1457.218us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.300s 4614.470us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.300s 4614.470us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.300s 4614.470us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.300s 4614.470us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.300s 4614.470us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 105.410s 1457.218us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 105.410s 1457.218us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.880s 182.210us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.880s 182.210us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.880s 182.210us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 24.590s 463.899us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.300s 4614.470us 1 1 100.00
rom_ctrl_kmac_err_chk 7.510s 306.761us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.300s 4614.470us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.300s 4614.470us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.300s 4614.470us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.190s 858.834us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 105.410s 1457.218us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 241.420s 33238.252us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 35363770271522651909484834129126548261425478604363947901897882384482608790836 79
UVM_INFO @ 254766481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---