Simulation Results: rom_ctrl/64kb

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.97 %
  • code
  • 95.61 %
  • assert
  • 97.68 %
  • func
  • 97.61 %
  • line
  • 99.33 %
  • branch
  • 98.91 %
  • cond
  • 97.62 %
  • toggle
  • 95.54 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 9.230s 543.156us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.090s 294.629us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 8.620s 4130.875us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.400s 289.668us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.610s 1136.754us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.170s 770.991us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 8.620s 4130.875us 1 1 100.00
rom_ctrl_csr_aliasing 5.610s 1136.754us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.180s 228.227us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.020s 1028.861us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 6.630s 473.083us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 18.520s 1281.607us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.640s 559.373us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.850s 335.011us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.960s 318.738us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.960s 318.738us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.090s 294.629us 1 1 100.00
rom_ctrl_csr_rw 8.620s 4130.875us 1 1 100.00
rom_ctrl_csr_aliasing 5.610s 1136.754us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.680s 1070.688us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.090s 294.629us 1 1 100.00
rom_ctrl_csr_rw 8.620s 4130.875us 1 1 100.00
rom_ctrl_csr_aliasing 5.610s 1136.754us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.680s 1070.688us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.620s 16813.041us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 38.810s 2573.947us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 453.890s 2684.204us 1 1 100.00
rom_ctrl_tl_intg_err 101.580s 501.028us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 453.890s 2684.204us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 453.890s 2684.204us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.620s 16813.041us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.620s 16813.041us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.620s 16813.041us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.620s 16813.041us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.620s 16813.041us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 453.890s 2684.204us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 453.890s 2684.204us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 9.230s 543.156us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 9.230s 543.156us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 9.230s 543.156us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 101.580s 501.028us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.620s 16813.041us 1 1 100.00
rom_ctrl_kmac_err_chk 14.640s 559.373us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.620s 16813.041us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.620s 16813.041us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 108.620s 16813.041us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 38.810s 2573.947us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 453.890s 2684.204us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 40.010s 1425.157us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 19981556765427679018472475484029129789110678116858595136599963103415560497131 79
UVM_INFO @ 473083247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---