Simulation Results: rstmgr

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.68 %
  • code
  • 99.26 %
  • assert
  • 98.53 %
  • func
  • 98.26 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.54 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.390s 259.329us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.760s 98.409us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.800s 71.120us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 7.430s 2860.337us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.480s 161.702us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.000s 185.319us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.800s 71.120us 1 1 100.00
rstmgr_csr_aliasing 1.480s 161.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.880s 147.948us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.330s 162.458us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.790s 96.991us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.920s 2246.293us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.920s 2246.293us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.920s 2246.293us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.920s 2246.293us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 43.500s 18963.307us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.820s 69.105us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.040s 92.653us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.040s 92.653us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.760s 98.409us 1 1 100.00
rstmgr_csr_rw 0.800s 71.120us 1 1 100.00
rstmgr_csr_aliasing 1.480s 161.702us 1 1 100.00
rstmgr_same_csr_outstanding 1.100s 88.199us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.760s 98.409us 1 1 100.00
rstmgr_csr_rw 0.800s 71.120us 1 1 100.00
rstmgr_csr_aliasing 1.480s 161.702us 1 1 100.00
rstmgr_same_csr_outstanding 1.100s 88.199us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 9.890s 8639.185us 1 1 100.00
rstmgr_tl_intg_err 2.610s 933.489us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 9.890s 8639.185us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 9.890s 8639.185us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.610s 933.489us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.240s 200.620us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.360s 2567.175us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.060s 301.610us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 9.890s 8639.185us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.800s 71.120us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.800s 71.120us 1 1 100.00