Simulation Results: rstmgr_cnsty_chk

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Validation stages
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rstmgr_cnsty_chk_test 2.230s 11203.340us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *)) 1 test run
rstmgr_cnsty_chk_test 98661212023413317867656375133746555225888514767303948982337844412749787701744 175
UVM_INFO @ 2040729634 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 2061049634 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 2081369634 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 2101689634 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
Job cancelled because all of its dependencies failed or were killed. 1 test run
rstmgr_cnsty_chk None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
rstmgr_cnsty_chk None None