Simulation Results: rv_timer

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.31 %
  • code
  • 94.16 %
  • assert
  • 98.41 %
  • func
  • 87.35 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 76.63 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.650s 26.643us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.540s 28.032us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.550s 13.216us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.330s 624.855us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.780s 63.117us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.800s 22.897us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.550s 13.216us 1 1 100.00
rv_timer_csr_aliasing 0.780s 63.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.620s 241.870us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.600s 373.004us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 401.290s 994695.752us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 401.290s 994695.752us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.160s 1627.824us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.540s 132.226us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.600s 19.663us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.180s 86.218us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.180s 86.218us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.540s 28.032us 1 1 100.00
rv_timer_csr_rw 0.550s 13.216us 1 1 100.00
rv_timer_csr_aliasing 0.780s 63.117us 1 1 100.00
rv_timer_same_csr_outstanding 0.660s 100.211us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.540s 28.032us 1 1 100.00
rv_timer_csr_rw 0.550s 13.216us 1 1 100.00
rv_timer_csr_aliasing 0.780s 63.117us 1 1 100.00
rv_timer_same_csr_outstanding 0.660s 100.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.660s 145.446us 1 1 100.00
rv_timer_tl_intg_err 1.170s 176.904us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.170s 176.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.610s 77.252us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.190s 42.221us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 7.750s 990.531us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 95825235681613040922227634820353335749298031662817958703050348841276245796303 75
UVM_INFO @ 77251670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 11198957563273427822908077346091769964281288314410195665463931608372410507249 75
UVM_INFO @ 241870391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 114581762657917685433393409521747482541520389358871067394096733040307572959551 75
UVM_INFO @ 42221131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---