Simulation Results: spi_device/1r1w

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.43 %
  • code
  • 90.70 %
  • assert
  • 95.40 %
  • func
  • 70.19 %
  • line
  • 98.86 %
  • branch
  • 98.14 %
  • cond
  • 96.09 %
  • toggle
  • 71.04 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 39.220s 18058.452us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.910s 65.012us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.860s 498.512us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 10.140s 2265.563us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 11.450s 374.423us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.720s 137.934us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.860s 498.512us 1 1 100.00
spi_device_csr_aliasing 11.450s 374.423us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.760s 15.592us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.130s 73.625us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.690s 28.795us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.800s 1.120us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.760s 14.610us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.980s 25.483us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.980s 25.483us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 9.600s 50591.574us 1 1 100.00
spi_device_tpm_sts_read 0.770s 51.060us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 4.490s 533.493us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.910s 3202.205us 1 1 100.00
spi_device_flash_all 33.430s 11984.335us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.300s 1015.731us 1 1 100.00
spi_device_flash_all 33.430s 11984.335us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.300s 1015.731us 1 1 100.00
spi_device_flash_all 33.430s 11984.335us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 33.430s 11984.335us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 6.350s 4540.208us 1 1 100.00
spi_device_flash_all 33.430s 11984.335us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 6.350s 4540.208us 1 1 100.00
spi_device_flash_all 33.430s 11984.335us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 6.350s 4540.208us 1 1 100.00
spi_device_flash_all 33.430s 11984.335us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 6.350s 4540.208us 1 1 100.00
spi_device_flash_all 33.430s 11984.335us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 6.350s 4540.208us 1 1 100.00
spi_device_flash_all 33.430s 11984.335us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 4.750s 1098.894us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 7.310s 1684.373us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 7.310s 1684.373us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 7.310s 1684.373us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 3.380s 137.128us 1 1 100.00
spi_device_read_buffer_direct 3.590s 3236.723us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 7.310s 1684.373us 1 1 100.00
spi_device_flash_all 33.430s 11984.335us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 33.430s 11984.335us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 33.430s 11984.335us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 13.640s 11289.748us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 13.640s 11289.748us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 87.880s 41527.690us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 39.220s 18058.452us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 38.930s 9145.859us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 75.450s 36788.801us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.680s 41.050us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.750s 47.998us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.270s 549.055us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.270s 549.055us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.910s 65.012us 1 1 100.00
spi_device_csr_rw 1.860s 498.512us 1 1 100.00
spi_device_csr_aliasing 11.450s 374.423us 1 1 100.00
spi_device_same_csr_outstanding 3.570s 827.784us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.910s 65.012us 1 1 100.00
spi_device_csr_rw 1.860s 498.512us 1 1 100.00
spi_device_csr_aliasing 11.450s 374.423us 1 1 100.00
spi_device_same_csr_outstanding 3.570s 827.784us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.840s 36.016us 1 1 100.00
spi_device_tl_intg_err 15.380s 2007.584us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 15.380s 2007.584us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 40313446667535715182681345342454435180062070871567768722931169022551344793431 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 844713 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 844713 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[942])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 15532953533157514781070557996203040635690896545974520207852016812079587996387 76
UVM_ERROR @ 12413003 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x80594c [100000000101100101001100] vs 0x0 [0])
UVM_ERROR @ 12414003 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x381a67 [1110000001101001100111] vs 0x0 [0])
UVM_ERROR @ 12514003 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4bdf5c [10010111101111101011100] vs 0x0 [0])
UVM_ERROR @ 12550003 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x473959 [10001110011100101011001] vs 0x0 [0])