Simulation Results: sram_ctrl/ret

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.19 %
  • code
  • 82.35 %
  • assert
  • 97.26 %
  • func
  • 93.96 %
  • block
  • 93.76 %
  • line
  • 94.91 %
  • branch
  • 89.51 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 214.152us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 17.839us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.163us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 143.256us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.896us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 149.733us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 18.163us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.896us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.000s 213.284us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 190.916us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 3.000s 499.019us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 81.000s 1651.937us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 8.000s 507.640us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 10.000s 359.063us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.000s 502.568us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 13.000s 1309.778us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 70.230us 1 1 100.00
sram_ctrl_partial_access_b2b 157.000s 18451.193us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 98.930us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 51.540us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 95.060us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 3683.227us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 29.165us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 28.000s 3358.422us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 25.522us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 38.748us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 38.748us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 17.839us 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.163us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.896us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 19.864us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 17.839us 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.163us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.896us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 19.864us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 441.187us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1725.008us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 242.181us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1725.008us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 242.181us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 3683.227us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 3683.227us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.163us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 13.000s 1309.778us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 1309.778us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 1309.778us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.000s 502.568us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 156.294us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 441.187us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 267.007us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 214.152us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 214.152us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 13.000s 1309.778us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1725.008us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.000s 502.568us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1725.008us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1725.008us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 214.152us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1725.008us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 6.000s 2599.873us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 3062719141896217709586254970537529325009073177852897223536588614242147410172 86
UVM_INFO @ 98930463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 41786616037177350260065168599780973132077105937458326208982049766373900530997 86
UVM_INFO @ 51540482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 27464952213822781452622995854741642768607282725670110601767079591882723389024 86
UVM_INFO @ 95059799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---