Simulation Results: sysrst_ctrl

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.87 %
  • code
  • 93.12 %
  • assert
  • 94.92 %
  • func
  • 57.57 %
  • line
  • 97.69 %
  • branch
  • 97.70 %
  • cond
  • 95.48 %
  • toggle
  • 99.09 %
  • FSM
  • 75.64 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 2.440s 2118.023us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.740s 2493.159us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 4.620s 2424.955us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.730s 2330.897us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 9.690s 6047.654us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 5.120s 2029.160us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 14.220s 26547.780us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 7.750s 2809.251us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.470s 2080.126us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 5.120s 2029.160us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.750s 2809.251us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 189.730s 124862.639us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 107.180s 67926.392us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 6.170s 3490.819us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 4.880s 4216.474us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.880s 2522.494us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.570s 2190.696us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1.970s 3018.872us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.260s 2608.856us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 23.360s 1290359.092us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 16.290s 39637.190us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 7.630s 9441.264us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.490s 2030.299us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.650s 2052.834us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.390s 2084.444us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.390s 2084.444us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 9.690s 6047.654us 1 1 100.00
sysrst_ctrl_csr_rw 5.120s 2029.160us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.750s 2809.251us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.130s 7679.119us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 9.690s 6047.654us 1 1 100.00
sysrst_ctrl_csr_rw 5.120s 2029.160us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.750s 2809.251us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.130s 7679.119us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 4.720s 42726.116us 1 1 100.00
sysrst_ctrl_tl_intg_err 36.070s 22261.330us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 36.070s 22261.330us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 4.830s 5310.683us 1 1 100.00