Simulation Results: uart

 
13/07/2026 15:30:34 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.09 %
  • code
  • 95.15 %
  • assert
  • 97.12 %
  • func
  • 53.99 %
  • line
  • 98.86 %
  • branch
  • 96.50 %
  • cond
  • 93.93 %
  • toggle
  • 91.32 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 8.990s 5672.634us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.630s 15.743us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.590s 15.880us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.980s 363.969us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.720s 44.753us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.830s 18.484us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.590s 15.880us 1 1 100.00
uart_csr_aliasing 0.720s 44.753us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 77.390s 60988.675us 1 1 100.00
parity 2 2 100.00
uart_smoke 8.990s 5672.634us 1 1 100.00
uart_tx_rx 77.390s 60988.675us 1 1 100.00
parity_error 2 2 100.00
uart_intr 16.090s 17255.148us 1 1 100.00
uart_rx_parity_err 263.110s 164062.810us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 77.390s 60988.675us 1 1 100.00
uart_intr 16.090s 17255.148us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 45.950s 53330.789us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 10.440s 30722.503us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 48.740s 47506.557us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 16.090s 17255.148us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 16.090s 17255.148us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 16.090s 17255.148us 1 1 100.00
perf 1 1 100.00
uart_perf 556.970s 24210.854us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 4.640s 4584.938us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 4.640s 4584.938us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 5.440s 3577.802us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 1.750s 4806.733us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.170s 1334.857us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 3.610s 3352.923us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 117.130s 130714.821us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 159.000s 234200.425us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.660s 13.706us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.650s 18.442us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.430s 696.378us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.430s 696.378us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.630s 15.743us 1 1 100.00
uart_csr_rw 0.590s 15.880us 1 1 100.00
uart_csr_aliasing 0.720s 44.753us 1 1 100.00
uart_same_csr_outstanding 0.730s 22.217us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.630s 15.743us 1 1 100.00
uart_csr_rw 0.590s 15.880us 1 1 100.00
uart_csr_aliasing 0.720s 44.753us 1 1 100.00
uart_same_csr_outstanding 0.730s 22.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.910s 269.291us 1 1 100.00
uart_tl_intg_err 0.890s 185.220us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.890s 185.220us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 22.760s 11570.966us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_noise_filter 98251909035801612858821008555625709715740544014891245846945223686199427613542 74
UVM_ERROR @ 98867815 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 142785887 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 142785887 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 149650690 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_stress_all 113844923597114488781923961348817701493750467623574303155211277914114284961218 84
UVM_ERROR @ 230041114785 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 230041329072 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (198 [0xc6] vs 253 [0xfd]) reg name: uart_reg_block.rdata
UVM_ERROR @ 230485260307 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 230485260307 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0