Simulation Results

Simulation Results: adc_ctrl

14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
66.09 %

code
94.30 %

assert
92.38 %

func
11.59 %

line
98.68 %

branch
97.15 %

cond
86.97 %

toggle
99.53 %

FSM
89.19 %

Validation stages

V1		100.00%
V2		57.89%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	adc_ctrl_smoke	2.670s	5973.397us	1	1	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	1.420s	1202.870us	1	1	100.00
csr_rw				1	1	100.00
	adc_ctrl_csr_rw	0.760s	561.257us	1	1	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	59.230s	26345.658us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	1.300s	678.030us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	1.370s	498.298us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	adc_ctrl_csr_rw	0.760s	561.257us	1	1	100.00
	adc_ctrl_csr_aliasing	1.300s	678.030us	1	1	100.00

11/19 passed

57.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	1	0.00
	adc_ctrl_filters_polled	0.890s	500.755us	0	1	0.00
filters_polled_fixed				0	1	0.00
	adc_ctrl_filters_polled_fixed	0.740s	504.926us	0	1	0.00
filters_interrupt				0	1	0.00
	adc_ctrl_filters_interrupt	0.690s	392.130us	0	1	0.00
filters_interrupt_fixed				0	1	0.00
	adc_ctrl_filters_interrupt_fixed	0.860s	395.978us	0	1	0.00
filters_wakeup				0	1	0.00
	adc_ctrl_filters_wakeup	0.950s	291.874us	0	1	0.00
filters_wakeup_fixed				0	1	0.00
	adc_ctrl_filters_wakeup_fixed	0.760s	402.637us	0	1	0.00
filters_both				0	1	0.00
	adc_ctrl_filters_both	1.040s	372.690us	0	1	0.00
clock_gating				0	1	0.00
	adc_ctrl_clock_gating	0.980s	338.106us	0	1	0.00
poweron_counter				1	1	100.00
	adc_ctrl_poweron_counter	3.400s	3889.549us	1	1	100.00
lowpower_counter				1	1	100.00
	adc_ctrl_lowpower_counter	13.960s	42488.445us	1	1	100.00
fsm_reset				1	1	100.00
	adc_ctrl_fsm_reset	69.750s	89254.898us	1	1	100.00
stress_all				1	1	100.00
	adc_ctrl_stress_all	51.300s	72846.217us	1	1	100.00
alert_test				1	1	100.00
	adc_ctrl_alert_test	0.740s	523.724us	1	1	100.00
intr_test				1	1	100.00
	adc_ctrl_intr_test	0.690s	533.307us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	adc_ctrl_tl_errors	2.400s	684.487us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	adc_ctrl_tl_errors	2.400s	684.487us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	adc_ctrl_csr_hw_reset	1.420s	1202.870us	1	1	100.00
	adc_ctrl_csr_rw	0.760s	561.257us	1	1	100.00
	adc_ctrl_csr_aliasing	1.300s	678.030us	1	1	100.00
	adc_ctrl_same_csr_outstanding	5.100s	4748.648us	1	1	100.00
tl_d_partial_access				4	4	100.00
	adc_ctrl_csr_hw_reset	1.420s	1202.870us	1	1	100.00
	adc_ctrl_csr_rw	0.760s	561.257us	1	1	100.00
	adc_ctrl_csr_aliasing	1.300s	678.030us	1	1	100.00
	adc_ctrl_same_csr_outstanding	5.100s	4748.648us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	adc_ctrl_sec_cm	5.840s	7728.091us	1	1	100.00
	adc_ctrl_tl_intg_err	2.230s	4838.183us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	adc_ctrl_tl_intg_err	2.230s	4838.183us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	adc_ctrl_stress_all_with_rand_reset	3.820s	1192.943us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				8 test runs
	adc_ctrl_filters_polled	2551835623898650692251361513347792113004623186073736995399491071252732003442	386	UVM_INFO @ 500755060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	16679880278868258184543991113323148949863107645499487886376785507664696429742	386	UVM_INFO @ 504926038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	48211923704057275084240284435425953554326996236390950689025329051151373306478	386	UVM_INFO @ 392130151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	44418885249650811798350745715694147220837889379462729953709329431453441137094	386	UVM_INFO @ 395977821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	40836367260045298941798551784931894560810561697263193117468267816379695727131	386	UVM_INFO @ 291874230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	36610639902233580309347527571903898195988157391659162944313665504978762824423	386	UVM_INFO @ 402636540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	32457703304373141762920182417355308428650717663892779350300002779201878042603	386	UVM_INFO @ 338106351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	20338721267651229407959306755574997893879494889827561267355381141084419997723	386	UVM_INFO @ 372689502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---