Simulation Results: aes/masked

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.80 %
  • code
  • 93.63 %
  • assert
  • 98.38 %
  • func
  • 74.38 %
  • block
  • 94.31 %
  • line
  • 95.92 %
  • branch
  • 87.30 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 111.399us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 71.826us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 80.846us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 63.036us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 248.849us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 411.020us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 55.427us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 63.036us 1 1 100.00
aes_csr_aliasing 3.000s 411.020us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 71.826us 1 1 100.00
aes_config_error 4.000s 169.761us 1 1 100.00
aes_stress 2.000s 95.088us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 71.826us 1 1 100.00
aes_config_error 4.000s 169.761us 1 1 100.00
aes_stress 2.000s 95.088us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 95.088us 1 1 100.00
aes_b2b 4.000s 173.218us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 95.088us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 71.826us 1 1 100.00
aes_config_error 4.000s 169.761us 1 1 100.00
aes_stress 2.000s 95.088us 1 1 100.00
aes_alert_reset 5.000s 2549.737us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 85.012us 1 1 100.00
aes_config_error 4.000s 169.761us 1 1 100.00
aes_alert_reset 5.000s 2549.737us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 90.277us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 9.000s 276.105us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 5.000s 2549.737us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 95.088us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 95.088us 1 1 100.00
aes_sideload 4.000s 113.755us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 79.289us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 20.000s 373.060us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 241.898us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 93.607us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 93.607us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 80.846us 1 1 100.00
aes_csr_rw 1.000s 63.036us 1 1 100.00
aes_csr_aliasing 3.000s 411.020us 1 1 100.00
aes_same_csr_outstanding 1.000s 64.810us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 80.846us 1 1 100.00
aes_csr_rw 1.000s 63.036us 1 1 100.00
aes_csr_aliasing 3.000s 411.020us 1 1 100.00
aes_same_csr_outstanding 1.000s 64.810us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 227.557us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 99.535us 0 1 0.00
aes_control_fi 3.000s 100.342us 1 1 100.00
aes_cipher_fi 3.000s 158.256us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 88.416us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 88.416us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 88.416us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 88.416us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 115.147us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 301.889us 1 1 100.00
aes_tl_intg_err 2.000s 1036.632us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 1036.632us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 5.000s 2549.737us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 88.416us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 88.416us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 71.826us 1 1 100.00
aes_stress 2.000s 95.088us 1 1 100.00
aes_alert_reset 5.000s 2549.737us 1 1 100.00
aes_core_fi 2.000s 105.665us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 4.000s 169.761us 1 1 100.00
aes_stress 2.000s 95.088us 1 1 100.00
aes_core_fi 2.000s 105.665us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 88.416us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 81.313us 1 1 100.00
aes_stress 2.000s 95.088us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 95.088us 1 1 100.00
aes_sideload 4.000s 113.755us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 81.313us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 81.313us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 81.313us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 81.313us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 81.313us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 95.088us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 95.088us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 99.535us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 99.535us 0 1 0.00
aes_control_fi 3.000s 100.342us 1 1 100.00
aes_cipher_fi 3.000s 158.256us 1 1 100.00
aes_ctr_fi 1.000s 58.573us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 99.535us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 99.535us 0 1 0.00
aes_control_fi 3.000s 100.342us 1 1 100.00
aes_cipher_fi 3.000s 158.256us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 158.256us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 99.535us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 99.535us 0 1 0.00
aes_control_fi 3.000s 100.342us 1 1 100.00
aes_ctr_fi 1.000s 58.573us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 99.535us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 99.535us 0 1 0.00
aes_control_fi 3.000s 100.342us 1 1 100.00
aes_cipher_fi 3.000s 158.256us 1 1 100.00
aes_ctr_fi 1.000s 58.573us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 5.000s 2549.737us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 99.535us 0 1 0.00
aes_control_fi 3.000s 100.342us 1 1 100.00
aes_cipher_fi 3.000s 158.256us 1 1 100.00
aes_ctr_fi 1.000s 58.573us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 99.535us 0 1 0.00
aes_control_fi 3.000s 100.342us 1 1 100.00
aes_cipher_fi 3.000s 158.256us 1 1 100.00
aes_ctr_fi 1.000s 58.573us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 99.535us 0 1 0.00
aes_control_fi 3.000s 100.342us 1 1 100.00
aes_ctr_fi 1.000s 58.573us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 99.535us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 99.535us 0 1 0.00
aes_control_fi 3.000s 100.342us 1 1 100.00
aes_cipher_fi 3.000s 158.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 5.534us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 24506147907844518869485300745635362890680118722622563213285733349539207748943 5576
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all 79761433473740230162364035306476734478549350832701802603432259338399524105917 84934
UVM_INFO @ 373059626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 12607871423005317558478089838382350090970244785182744669866817780764241865783 135
UVM_INFO @ 5533645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---