Simulation Results: aes/unmasked

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.64 %
  • code
  • 88.97 %
  • assert
  • 97.73 %
  • func
  • 73.23 %
  • block
  • 89.38 %
  • line
  • 91.88 %
  • branch
  • 79.35 %
  • toggle
  • 97.99 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 79.824us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 153.297us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 59.912us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 277.639us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 3999.716us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 132.829us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 68.746us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 277.639us 1 1 100.00
aes_csr_aliasing 2.000s 132.829us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 153.297us 1 1 100.00
aes_config_error 2.000s 98.366us 1 1 100.00
aes_stress 1.000s 107.211us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 153.297us 1 1 100.00
aes_config_error 2.000s 98.366us 1 1 100.00
aes_stress 1.000s 107.211us 1 1 100.00
back2back 2 2 100.00
aes_stress 1.000s 107.211us 1 1 100.00
aes_b2b 5.000s 370.583us 1 1 100.00
backpressure 1 1 100.00
aes_stress 1.000s 107.211us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 153.297us 1 1 100.00
aes_config_error 2.000s 98.366us 1 1 100.00
aes_stress 1.000s 107.211us 1 1 100.00
aes_alert_reset 2.000s 87.011us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 64.436us 1 1 100.00
aes_config_error 2.000s 98.366us 1 1 100.00
aes_alert_reset 2.000s 87.011us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 78.077us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 558.762us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 87.011us 1 1 100.00
stress 1 1 100.00
aes_stress 1.000s 107.211us 1 1 100.00
sideload 2 2 100.00
aes_stress 1.000s 107.211us 1 1 100.00
aes_sideload 2.000s 99.294us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 102.960us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10802.112s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 78.032us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 191.780us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 191.780us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 59.912us 1 1 100.00
aes_csr_rw 2.000s 277.639us 1 1 100.00
aes_csr_aliasing 2.000s 132.829us 1 1 100.00
aes_same_csr_outstanding 2.000s 169.393us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 59.912us 1 1 100.00
aes_csr_rw 2.000s 277.639us 1 1 100.00
aes_csr_aliasing 2.000s 132.829us 1 1 100.00
aes_same_csr_outstanding 2.000s 169.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 2.000s 48.708us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 3.000s 160.272us 0 1 0.00
aes_control_fi 1.000s 122.775us 1 1 100.00
aes_cipher_fi 2.000s 69.890us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 111.893us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 111.893us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 111.893us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 111.893us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 242.679us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 1298.802us 1 1 100.00
aes_tl_intg_err 3.000s 543.203us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 543.203us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 87.011us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 111.893us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 111.893us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 153.297us 1 1 100.00
aes_stress 1.000s 107.211us 1 1 100.00
aes_alert_reset 2.000s 87.011us 1 1 100.00
aes_core_fi 2.000s 159.569us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 98.366us 1 1 100.00
aes_stress 1.000s 107.211us 1 1 100.00
aes_core_fi 2.000s 159.569us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 111.893us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 82.262us 1 1 100.00
aes_stress 1.000s 107.211us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 1.000s 107.211us 1 1 100.00
aes_sideload 2.000s 99.294us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 82.262us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 82.262us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 82.262us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 82.262us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 82.262us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 1.000s 107.211us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 1.000s 107.211us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 160.272us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 160.272us 0 1 0.00
aes_control_fi 1.000s 122.775us 1 1 100.00
aes_cipher_fi 2.000s 69.890us 1 1 100.00
aes_ctr_fi 2.000s 61.577us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 160.272us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 160.272us 0 1 0.00
aes_control_fi 1.000s 122.775us 1 1 100.00
aes_cipher_fi 2.000s 69.890us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 69.890us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 160.272us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 160.272us 0 1 0.00
aes_control_fi 1.000s 122.775us 1 1 100.00
aes_ctr_fi 2.000s 61.577us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 160.272us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 160.272us 0 1 0.00
aes_control_fi 1.000s 122.775us 1 1 100.00
aes_cipher_fi 2.000s 69.890us 1 1 100.00
aes_ctr_fi 2.000s 61.577us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 87.011us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 160.272us 0 1 0.00
aes_control_fi 1.000s 122.775us 1 1 100.00
aes_cipher_fi 2.000s 69.890us 1 1 100.00
aes_ctr_fi 2.000s 61.577us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 160.272us 0 1 0.00
aes_control_fi 1.000s 122.775us 1 1 100.00
aes_cipher_fi 2.000s 69.890us 1 1 100.00
aes_ctr_fi 2.000s 61.577us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 160.272us 0 1 0.00
aes_control_fi 1.000s 122.775us 1 1 100.00
aes_ctr_fi 2.000s 61.577us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 160.272us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 160.272us 0 1 0.00
aes_control_fi 1.000s 122.775us 1 1 100.00
aes_cipher_fi 2.000s 69.890us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 38.630us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 47111791238208723249079651537837097454404107943539473160287405159627019516684 3486
UVM_INFO @ 48707565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 69314316575967429049700951694216494587804170979317328686323929869236357730070 8401
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
Job timed out after * minutes 1 test run
aes_stress_all 104149218181013297676056779879318197242226365542860062863076561333102726722995 None
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 72076034882005612720673892512634667313972131041037204524211036934867661914098 148
UVM_INFO @ 38630330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---