Simulation Results: alert_handler

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.89 %
  • code
  • 91.46 %
  • assert
  • 98.40 %
  • func
  • 79.80 %
  • line
  • 99.72 %
  • branch
  • 97.99 %
  • cond
  • 91.05 %
  • toggle
  • 89.52 %
  • FSM
  • 79.03 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 39.610s 1285.513us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 5.900s 467.930us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.350s 133.888us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 306.900s 18752.653us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 151.160s 3675.968us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.720s 56.835us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.350s 133.888us 1 1 100.00
alert_handler_csr_aliasing 151.160s 3675.968us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 92.360s 2319.534us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 4.250s 357.918us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 822.890s 32883.935us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 3.810s 139.714us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 39.610s 1285.513us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 33.220s 4024.884us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 17.420s 545.513us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 24.920s 3927.111us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 2049.010s 239171.156us 1 1 100.00
alert_handler_lpg_stub_clk 2158.820s 280439.804us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 834.120s 29503.351us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 3.730s 379.668us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.540s 167.119us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.120s 31.168us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 5.820s 93.817us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 5.820s 93.817us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 5.900s 467.930us 1 1 100.00
alert_handler_csr_rw 3.350s 133.888us 1 1 100.00
alert_handler_csr_aliasing 151.160s 3675.968us 1 1 100.00
alert_handler_same_csr_outstanding 12.130s 795.695us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 5.900s 467.930us 1 1 100.00
alert_handler_csr_rw 3.350s 133.888us 1 1 100.00
alert_handler_csr_aliasing 151.160s 3675.968us 1 1 100.00
alert_handler_same_csr_outstanding 12.130s 795.695us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 77.380s 2110.817us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 77.380s 2110.817us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 77.380s 2110.817us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 77.380s 2110.817us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 662.570s 64035.048us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 9.080s 302.911us 1 1 100.00
alert_handler_tl_intg_err 27.120s 2493.352us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 27.120s 2493.352us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 77.380s 2110.817us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 39.610s 1285.513us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 39.610s 1285.513us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 39.610s 1285.513us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 39.610s 1285.513us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 3.810s 139.714us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 2049.010s 239171.156us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 3.810s 139.714us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 822.890s 32883.935us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 822.890s 32883.935us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.080s 302.911us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.080s 302.911us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.080s 302.911us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.080s 302.911us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 9.080s 302.911us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.080s 302.911us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.080s 302.911us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.080s 302.911us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 9.080s 302.911us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 64.580s 2263.617us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 94068485673543731411579844140279216455726771773514043383757490810852676901047 84
UVM_INFO @ 3927111314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 136142038031835426973965811924908066975821556199326561738098668070337692315 164
UVM_INFO @ 379667619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 41174406091680555137987829284564876504636835515896445384023511581049642089494 150
UVM_INFO @ 2263617123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---