Simulation Results: chip

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.88 %
  • code
  • 84.33 %
  • assert
  • 97.49 %
  • func
  • 39.83 %
  • line
  • 94.47 %
  • branch
  • 93.78 %
  • cond
  • 89.10 %
  • toggle
  • 87.17 %
  • FSM
  • 57.14 %
Validation stages
V1
100.00%
V2
76.17%
V2S
100.00%
V3
61.54%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 128.720s 3263.953us 1 1 100.00
chip_sw_example_rom 73.560s 2459.348us 1 1 100.00
chip_sw_example_manufacturer 111.170s 2411.842us 1 1 100.00
chip_sw_example_concurrency 175.060s 2492.483us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 174.970s 5761.929us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 369.970s 5193.978us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 512.720s 6526.746us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3502.400s 28311.504us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
chip_csr_mem_rw_with_rand_reset 359.430s 6988.520us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3502.400s 28311.504us 1 1 100.00
chip_csr_rw 369.970s 5193.978us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 5.190s 172.611us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 336.690s 4278.783us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 336.690s 4278.783us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 336.690s 4278.783us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 379.830s 4550.846us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 379.830s 4550.846us 1 1 100.00
chip_sw_uart_tx_rx_idx1 329.360s 4656.738us 1 1 100.00
chip_sw_uart_tx_rx_idx2 364.860s 4587.377us 1 1 100.00
chip_sw_uart_tx_rx_idx3 375.670s 4271.389us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 363.250s 4568.769us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1125.660s 8893.502us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 271.710s 3909.285us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 174.070s 4585.986us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 174.070s 4585.986us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 203.580s 3619.887us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 329.090s 5943.559us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 159.490s 3064.677us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 149.170s 3615.188us 1 1 100.00
chip_tap_straps_testunlock0 210.120s 4284.343us 1 1 100.00
chip_tap_straps_rma 653.440s 10867.386us 1 1 100.00
chip_tap_straps_prod 749.440s 11786.793us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 589.040s 6267.728us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 589.040s 6267.728us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 597.160s 8562.270us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 750.140s 10020.494us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 372.380s 4254.557us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 501.610s 5773.518us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4079.120s 18483.241us 1 1 100.00
chip_sw_aes_enc_jitter_en 173.400s 3061.993us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 538.320s 6173.033us 1 1 100.00
chip_sw_hmac_enc_jitter_en 148.110s 3309.918us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1474.850s 12371.013us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 201.880s 3559.628us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 289.610s 4555.131us 1 1 100.00
chip_sw_clkmgr_jitter 132.610s 3106.515us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 220.490s 3202.657us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 466.650s 9108.444us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 287.760s 5314.979us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 180.230s 3138.476us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 287.760s 5314.979us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 172.370s 3489.711us 1 1 100.00
chip_sw_aes_smoketest 203.370s 3250.162us 1 1 100.00
chip_sw_aon_timer_smoketest 180.240s 3435.771us 1 1 100.00
chip_sw_clkmgr_smoketest 169.010s 3007.410us 1 1 100.00
chip_sw_csrng_smoketest 145.870s 3209.131us 1 1 100.00
chip_sw_entropy_src_smoketest 658.200s 5809.044us 1 1 100.00
chip_sw_gpio_smoketest 183.910s 3500.255us 1 1 100.00
chip_sw_hmac_smoketest 190.910s 3049.961us 1 1 100.00
chip_sw_kmac_smoketest 144.870s 3014.770us 1 1 100.00
chip_sw_otbn_smoketest 1358.560s 10418.221us 1 1 100.00
chip_sw_pwrmgr_smoketest 277.930s 6358.794us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 326.300s 6859.702us 1 1 100.00
chip_sw_rv_plic_smoketest 163.380s 3030.194us 1 1 100.00
chip_sw_rv_timer_smoketest 179.000s 3762.070us 1 1 100.00
chip_sw_rstmgr_smoketest 118.220s 3219.393us 1 1 100.00
chip_sw_sram_ctrl_smoketest 177.510s 2728.826us 1 1 100.00
chip_sw_uart_smoketest 161.320s 3870.465us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 126.930s 2928.837us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 373.340s 4806.746us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8110.340s 59270.032us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3059.920s 14373.477us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 26.947s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 1150.890s 15058.631us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 908.120s 14817.200us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7220.510s 52358.167us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7278.010s 55248.290us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 63.010s 1948.577us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 63.010s 1948.577us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3502.400s 28311.504us 1 1 100.00
chip_same_csr_outstanding 1402.850s 15840.121us 1 1 100.00
chip_csr_hw_reset 174.970s 5761.929us 1 1 100.00
chip_csr_rw 369.970s 5193.978us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3502.400s 28311.504us 1 1 100.00
chip_same_csr_outstanding 1402.850s 15840.121us 1 1 100.00
chip_csr_hw_reset 174.970s 5761.929us 1 1 100.00
chip_csr_rw 369.970s 5193.978us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 16.330s 253.986us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 6.340s 42.738us 1 1 100.00
xbar_smoke_large_delays 31.780s 5613.172us 1 1 100.00
xbar_smoke_slow_rsp 47.120s 5329.792us 1 1 100.00
xbar_random_zero_delays 8.730s 125.092us 1 1 100.00
xbar_random_large_delays 146.390s 25320.390us 1 1 100.00
xbar_random_slow_rsp 145.530s 17985.191us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 14.540s 108.013us 1 1 100.00
xbar_error_and_unmapped_addr 21.640s 342.699us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 43.040s 1899.890us 1 1 100.00
xbar_error_and_unmapped_addr 21.640s 342.699us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 48.440s 1753.959us 1 1 100.00
xbar_access_same_device_slow_rsp 453.500s 55289.202us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 9.290s 370.010us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 127.990s 2208.723us 1 1 100.00
xbar_stress_all_with_error 122.890s 5376.136us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 48.910s 79.642us 1 1 100.00
xbar_stress_all_with_reset_error 30.860s 176.083us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3059.920s 14373.477us 1 1 100.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 537.200s 8603.853us 0 1 0.00
rom_e2e_shutdown_exception_c 0 1 0.00
rom_e2e_shutdown_exception_c 421.980s 6628.657us 0 1 0.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 30.785s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 15.570s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 14.452s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 8.072s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 12.816s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 36.436s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 10.046s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 30.119s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 21.431s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 14.893s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 137.740s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 48.952s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 43.163s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 25.981s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 33.605s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 20.290s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 19.340s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 22.450s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 26.170s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 19.430s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 22.510s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 18.250s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 19.620s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 19.370s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 19.310s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 18.530s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 18.500s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 21.820s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 19.650s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 18.980s 10.200us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 163.735s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 83.256s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 52.015s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 61.513s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 29.855s 0.000us 0 1 0.00
rom_e2e_keymgr_init 1 3 33.33
rom_e2e_keymgr_init_rom_ext_meas 5868.430s 28707.892us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 3215.180s 15591.544us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 3228.350s 15695.083us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3179.080s 15664.024us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3146.030s 35647.934us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3146.030s 35647.934us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 201.740s 3377.408us 1 1 100.00
chip_sw_aes_enc_jitter_en 173.400s 3061.993us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 163.360s 2635.176us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 194.920s 3408.917us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 701.720s 7685.505us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 171.490s 2495.927us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 306.610s 5324.791us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 398.560s 5265.604us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 425.400s 4825.376us 1 1 100.00
chip_plic_all_irqs_10 260.520s 3703.548us 1 1 100.00
chip_plic_all_irqs_20 287.620s 3949.270us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 217.710s 3507.327us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1280.870s 15106.638us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 200.360s 3989.220us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 189.060s 3409.646us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.157s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 667.520s 5973.053us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 996.110s 7756.921us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 798.760s 8490.900us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 9435.800s 255505.020us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 222.500s 3809.653us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 277.930s 6358.794us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 222.500s 3809.653us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 408.200s 7404.100us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 408.200s 7404.100us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 340.260s 8175.635us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 387.810s 5712.776us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 650.950s 5485.976us 1 1 100.00
chip_sw_aes_idle 194.920s 3408.917us 1 1 100.00
chip_sw_hmac_enc_idle 171.490s 2754.122us 1 1 100.00
chip_sw_kmac_idle 129.930s 2872.309us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 324.960s 5077.540us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 351.250s 4994.106us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 276.660s 5372.020us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 282.020s 5185.843us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 612.910s 9400.479us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 381.690s 4595.402us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 380.150s 4845.286us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 389.030s 4353.402us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 378.050s 4736.639us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 394.720s 4585.551us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 427.700s 4933.010us 1 1 100.00
chip_sw_ast_clk_outputs 597.160s 8562.270us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 328.470s 7246.025us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 389.030s 4353.402us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 378.050s 4736.639us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 372.380s 4254.557us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 501.610s 5773.518us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4079.120s 18483.241us 1 1 100.00
chip_sw_aes_enc_jitter_en 173.400s 3061.993us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 538.320s 6173.033us 1 1 100.00
chip_sw_hmac_enc_jitter_en 148.110s 3309.918us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1474.850s 12371.013us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 201.880s 3559.628us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 289.610s 4555.131us 1 1 100.00
chip_sw_clkmgr_jitter 132.610s 3106.515us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 136.850s 2825.865us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 361.100s 4240.671us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 616.830s 7234.894us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4463.310s 25046.035us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 160.630s 2970.906us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 189.250s 3471.690us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1201.260s 12347.675us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 209.140s 3225.189us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 323.040s 4725.314us 1 1 100.00
chip_sw_flash_init_reduced_freq 1088.240s 21781.578us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 14070.090s 156139.622us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 597.160s 8562.270us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 378.200s 4736.785us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 275.640s 3876.868us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 398.560s 5265.604us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 667.520s 5973.053us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2146.940s 24307.905us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 247.260s 3956.570us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 511.280s 6859.193us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 198.570s 3131.542us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2031.980s 12296.815us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 191.510s 2932.452us 1 1 100.00
chip_sw_edn_entropy_reqs 785.330s 6483.749us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 191.510s 2932.452us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2146.940s 24307.905us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 197.370s 3563.488us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1468.670s 22303.249us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 556.500s 5312.344us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 501.610s 5773.518us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 342.130s 4307.866us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 372.380s 4254.557us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3559.150s 44535.036us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1468.670s 22303.249us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 220.670s 3925.543us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1235.850s 9091.556us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 156.020s 2972.176us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3559.150s 44535.036us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 156.020s 2972.176us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 156.020s 2972.176us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 156.020s 2972.176us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 156.020s 2972.176us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 398.560s 5265.604us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 294.540s 11339.595us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 489.200s 5228.448us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 399.070s 5229.145us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 399.070s 5229.145us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 137.450s 3562.392us 1 1 100.00
chip_sw_hmac_enc_jitter_en 148.110s 3309.918us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 171.490s 2754.122us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1664.350s 11149.668us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1954.010s 12026.866us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 442.920s 4918.225us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 472.680s 5836.502us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 382.820s 4577.144us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 274.250s 3573.146us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1235.850s 9091.556us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1474.850s 12371.013us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1402.460s 10157.374us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 701.720s 7685.505us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 5535.600s 20018.635us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 171.220s 3192.112us 1 1 100.00
chip_sw_kmac_mode_kmac 209.640s 3394.664us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 201.880s 3559.628us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1235.850s 9091.556us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 677.730s 11508.664us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 167.770s 2393.169us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1384.100s 10193.676us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 129.930s 2872.309us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 306.610s 5324.791us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 149.170s 3615.188us 1 1 100.00
chip_tap_straps_rma 653.440s 10867.386us 1 1 100.00
chip_tap_straps_prod 749.440s 11786.793us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 144.540s 2803.779us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 677.730s 11508.664us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 677.730s 11508.664us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 677.730s 11508.664us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 649.580s 5844.065us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_sw_flash_ctrl_lc_rw_en 156.020s 2972.176us 0 1 0.00
chip_sw_flash_rma_unlocked 3559.150s 44535.036us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 182.310s 2877.309us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 395.120s 6592.526us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 538.410s 6948.987us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 560.310s 7630.318us 0 1 0.00
chip_sw_lc_ctrl_transition 677.730s 11508.664us 1 1 100.00
chip_sw_keymgr_key_derivation 1235.850s 9091.556us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 307.540s 8110.163us 1 1 100.00
chip_sw_sram_ctrl_execution_main 538.400s 10386.192us 1 1 100.00
chip_prim_tl_access 294.540s 11339.595us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 328.470s 7246.025us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 381.690s 4595.402us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 380.150s 4845.286us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 389.030s 4353.402us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 378.050s 4736.639us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 394.720s 4585.551us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 427.700s 4933.010us 1 1 100.00
chip_tap_straps_dev 149.170s 3615.188us 1 1 100.00
chip_tap_straps_rma 653.440s 10867.386us 1 1 100.00
chip_tap_straps_prod 749.440s 11786.793us 1 1 100.00
chip_rv_dm_lc_disabled 299.240s 10913.063us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 155.850s 3662.590us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 102.060s 3464.452us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 72.160s 2445.440us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 83.070s 3207.172us 1 1 100.00
chip_lc_test_locked 2 2 100.00
chip_sw_lc_walkthrough_testunlocks 1565.760s 32744.052us 1 1 100.00
chip_rv_dm_lc_disabled 299.240s 10913.063us 1 1 100.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 528.730s 7752.410us 0 1 0.00
chip_sw_lc_walkthrough_prod 855.630s 26383.621us 0 1 0.00
chip_sw_lc_walkthrough_prodend 709.570s 11836.803us 1 1 100.00
chip_sw_lc_walkthrough_rma 387.110s 6994.937us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1565.760s 32744.052us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 56.160s 2430.561us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 65.690s 2841.728us 1 1 100.00
rom_volatile_raw_unlock 24.847s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3929.340s 17389.573us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4079.120s 18483.241us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 650.950s 5485.976us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 650.950s 5485.976us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 650.950s 5485.976us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 326.150s 4228.215us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 677.730s 11508.664us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1468.670s 22303.249us 1 1 100.00
chip_sw_otbn_mem_scramble 326.150s 4228.215us 1 1 100.00
chip_sw_keymgr_key_derivation 1235.850s 9091.556us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 403.700s 5708.933us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 163.920s 2537.863us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1468.670s 22303.249us 1 1 100.00
chip_sw_otbn_mem_scramble 326.150s 4228.215us 1 1 100.00
chip_sw_keymgr_key_derivation 1235.850s 9091.556us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 403.700s 5708.933us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 163.920s 2537.863us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 677.730s 11508.664us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 334.240s 4548.856us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 144.540s 2803.779us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 182.310s 2877.309us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 395.120s 6592.526us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 538.410s 6948.987us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 560.310s 7630.318us 0 1 0.00
chip_sw_lc_ctrl_transition 677.730s 11508.664us 1 1 100.00
chip_prim_tl_access 294.540s 11339.595us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 294.540s 11339.595us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 880.870s 8542.803us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 212.000s 6920.481us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1096.920s 25685.676us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 240.410s 7237.310us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 410.710s 7494.137us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 443.980s 8366.540us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 794.530s 23885.704us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 259.300s 5152.267us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 408.200s 7404.100us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 905.850s 13168.913us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 275.260s 4382.005us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 212.000s 6920.481us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 307.690s 4935.945us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 472.610s 7769.601us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 384.090s 7189.936us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 176.460s 3238.541us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1283.750s 21580.733us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 646.290s 8248.902us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 894.720s 9445.410us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2184.190s 28350.552us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 202.270s 3482.862us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 398.560s 5265.604us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 307.540s 8110.163us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 307.540s 8110.163us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 894.720s 9445.410us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1283.750s 21580.733us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 275.260s 4382.005us 1 1 100.00
chip_sw_pwrmgr_smoketest 277.930s 6358.794us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 246.720s 4025.236us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 427.990s 6563.441us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 218.080s 4121.366us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1280.870s 15106.638us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 144.010s 2526.039us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 398.560s 5265.604us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 996.110s 7756.921us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 510.530s 4795.201us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 525.760s 4999.109us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 215.670s 3481.546us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 163.920s 2537.863us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 427.990s 6563.441us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 427.990s 6563.441us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 109.400s 3048.783us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 658.820s 10518.475us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1031.890s 14471.114us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 246.720s 4025.236us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 204.380s 3769.327us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 1459.060s 13177.042us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 653.440s 10867.386us 1 1 100.00
chip_rv_dm_lc_disabled 1 1 100.00
chip_rv_dm_lc_disabled 299.240s 10913.063us 1 1 100.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 425.400s 4825.376us 1 1 100.00
chip_plic_all_irqs_10 260.520s 3703.548us 1 1 100.00
chip_plic_all_irqs_20 287.620s 3949.270us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 188.090s 3435.899us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 176.900s 3648.340us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3059.920s 14373.477us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 243.530s 3617.666us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 188.980s 3463.156us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 266.990s 3549.373us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 171.990s 3550.971us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 403.700s 5708.933us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 289.610s 4555.131us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 351.280s 7955.419us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 448.720s 7268.406us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 538.400s 10386.192us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 398.560s 5265.604us 1 1 100.00
chip_sw_data_integrity_escalation 589.040s 6267.728us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 646.290s 8248.902us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1228.240s 23453.187us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 169.110s 3173.225us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 233.180s 4195.588us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 305.640s 4952.653us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1228.240s 23453.187us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1228.240s 23453.187us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2120.300s 20952.316us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2120.300s 20952.316us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 312.720s 6723.216us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3146.030s 35647.934us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 151.740s 3261.993us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 188.460s 3692.292us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 264.110s 3242.557us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 360.160s 4249.173us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1028.650s 8619.924us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5347.170s 31662.515us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1821.130s 12648.608us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 184.800s 3522.805us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 247.810s 3716.701us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 160.100s 2763.367us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9818.630s 67972.595us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1062.830s 6709.012us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 452.320s 6657.163us 0 1 0.00
rom_e2e_jtag_debug_dev 447.110s 6562.132us 0 1 0.00
rom_e2e_jtag_debug_rma 508.270s 7068.002us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 72.440s 2500.064us 0 1 0.00
rom_e2e_jtag_inject_dev 68.380s 2129.121us 0 1 0.00
rom_e2e_jtag_inject_rma 64.460s 2469.046us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 110.276s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 279.260s 3777.858us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 327.210s 3162.968us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 964.170s 5454.647us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1287.000s 9435.063us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 263.220s 2942.097us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 633.130s 5756.744us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 77.700s 2760.606us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 206.070s 3281.690us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 0 1 0.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 396.640s 7011.978us 0 1 0.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 290.150s 4743.095us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 894.720s 9445.410us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 452.320s 6657.163us 0 1 0.00
rom_e2e_jtag_debug_dev 447.110s 6562.132us 0 1 0.00
rom_e2e_jtag_debug_rma 508.270s 7068.002us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 437.900s 6509.921us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 398.560s 5265.604us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5492.640s 39161.039us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5492.640s 39161.039us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 232.380s 4012.043us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 379.830s 4550.846us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3039.210s 18425.501us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 209.260s 2856.866us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 20.020s 10.280us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 5.870s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 153.080s 2911.468us 1 1 100.00
chip_sw_otp_ctrl_descrambling 167.290s 2994.413us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 310.100s 4305.996us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.533s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 183.990s 2713.098us 1 1 100.00
ate_bootstrap_flash_erase 625.740s 10010.280us 0 1 0.00
ate_bootstrap_one_frame 6393.920s 43390.988us 1 1 100.00
ate_bootstrap_disjoint 9274.810s 79424.332us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 38706695990880899566161536154838930954481190997730789527323618514851326593654 None
---- STDERR ----
Another command (pid=2069474) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 87661510837667174614592036491255506769073993626824242561332739250734338814511 None
---- STDERR ----
Another command (pid=372615) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 79963689674318009429538064494188622648155843256604024755582089172813078231631 None
Another command (pid=601270) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=596055) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=640168) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 54143594563208575882590987413354782967364998900782525721069047376742616236560 None
Another command (pid=658770) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=655279) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=619858) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 41155010085535162528106516689622101386683038939758644163264647120912020454648 None
---- STDERR ----
Another command (pid=631633) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=589529) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 14835437595167480979441639259562001844112965073422927582236406810370057027263 None
Another command (pid=578177) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=617194) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=670378) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 73608006750289709019417794035287678783806103566370734192078045794619625871737 None
---- STDERR ----
Another command (pid=372615) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 15944244864980123590639466277566917604151262704491887124843542560150287802659 None
---- STDERR ----
Another command (pid=605563) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 30085707572039593955586500819627473712913143048987061925554117544200020185873 None
Another command (pid=655279) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=619858) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=661787) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 27094820517417438580425155834137605173210996199655244886021300393640999316478 None
Another command (pid=601270) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=596055) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=640168) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 111181798001064689910835644144173790730868206110279642518774429600807212773864 None
---- STDERR ----
Another command (pid=607604) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 59862855813838652117544854102821393239117052265916031794846246764981814852420 None
Another command (pid=590427) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=582523) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=459187) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 17613616506467462369310997638565269921270676072529779509621481727231387810963 None
Another command (pid=618468) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=645399) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=646844) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 33794830608949318365224896622624428752877348039312515666123444089245423733207 None
Another command (pid=646844) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=649011) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=658770) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 31913382174107457732410003526125782420640229958758274834961246021675971443296 None
Another command (pid=430697) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=586062) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=604099) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 49079772439036359118850256747752841258615804686835683616633858758830480463903 None
Another command (pid=589529) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=650526) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=636391) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 55254266647669239805554744584129588373346709345652338958216004082523930643917 None
Another command (pid=601270) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=596055) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=640168) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 73721625095399800251980703704806358207281108912867115679000426807986580684082 None
Another command (pid=556472) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=569303) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=559766) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 106301714988441164248382634735497139756062704216665199576374056976898525152550 None
Another command (pid=458639) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=477757) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=429497) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 114143922543762984832294028229510669588352135163222566894316148136856908651321 None
Another command (pid=459187) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=571441) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=584514) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 66638478316897840083878898018391278508234813140736159293602572218926049417828 None
Another command (pid=571730) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=461044) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=603521) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 46660491860336445874075539289953622935897481051626136670181534889828638491175 None
Another command (pid=443991) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=455192) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=457447) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 44358981253646660041645419732847708819998317519217001007082623610946444010823 None
Another command (pid=443991) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=455192) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=450347) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 46771323958650915255145596454648445168347895602676259004131410191052851679332 None
Another command (pid=562814) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=563271) is running. Waiting for it to complete on the server (server_pid=279417)...
Another command (pid=400526) is running. Waiting for it to complete on the server (server_pid=279417)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 7 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 36786193017353956273132566927790516719650475258940552994290633252097563764327 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 75583727195778823947544935546525885096399861681447621338016985402089417172061 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 29722465818626044714871098732067946552347768622356825247587466590847453082848 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 15863694133519901066435033542505481682057130124831351473993534457439619801455 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 83744374703312195353843235323473015540345002543534074615948005930387152343894 307
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 68917033309803590402528806099539883301883870077328204515291206820507996988005 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 1706400268907310896825544907184888048722333079064776066447083144407735355997 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 12078089841414382579914059056115530889162876735505713555031691385170611433835 368
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 13624611796959414023631587350243573471969613614920818357620289163146912744670 366
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 31475131760278561055178471700912387086961362592636883202005141034575007462746 365
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 22738882856322206418172751837530648003732215526099284590807555453667864854717 328
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 95669897235266988613293177153543079973340287646194246708236321042004305740479 327
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 114312461044650239119751443086705416546910707632874536897711618779984032022840 325
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 3 test runs
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 20183544495338649156416155179613152754965756970177314926970680930951363596136 314
UVM_ERROR @ 5152.267500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5152.267500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 39425055837451023205381725487945613565256796222474572434194131683490849709913 325
UVM_ERROR @ 7494.137500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7494.137500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 104027478648652534328990774873428575246424208931079152601126942771633994443209 319
UVM_ERROR @ 7404.100000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7404.100000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 17975332317069222938701006492352935478476575183927678055742161624322756242138 325
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 37859510947664879305159242214994389794627554476850870407892208195091863953035 326
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 74119156639873167747509335802718398031509476355687457464249722569642356029926 326
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 2 test runs
chip_sw_lc_walkthrough_dev 21077762969376999436405298277319065367486917906200857775108089138340053695174 369
UVM_INFO @ 7752.409716 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 99689171948422927312988538643113330911344171759166788664169497883086324299961 341
UVM_INFO @ 6994.937100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 2 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 44947652115226090172841478971163902438984355437226857940218720543068886780423 313
UVM_ERROR @ 3238.541274 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3238.541274 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 101080250850724678761227781178849944688395580597012338244375516738525732815453 329
UVM_ERROR @ 7769.600724 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 7769.600724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 63749072922132368919029923686211799395125138299833707361305976826795519338149 420
UVM_INFO @ 12026.866494 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 34111778076707218108552727739050803939406009785192943634168198026127521750026 338
UVM_INFO @ 20018.634940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 56936958197801656177835721581245410004540143787420148938210783739139852287024 364
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 20175536915973687986412307985726557587106058276011112609392179114682228527176 325
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 75115033911432744059954936755369086252683251754747511061621208055390571147440 368
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 106250686765745042452926455939276663814449989988654410895926274296133236656558 327
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 5576075958516298481315611110166365695125139230247405083896557717248544490439 301
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch 1 test run
chip_sw_spi_device_pass_through_collision 105561213119838074320689845948536723118534785592421998130942318677100786508700 329
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 179708435616697776453708065066126851362001890833544384889969772296948102768 309
UVM_INFO @ 2972.175924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 79348841591891999816910227937764035810345871527001161756300301096905179823774 342
UVM_INFO @ 7630.317752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 66443319968310745850163326613882895460295032250198927794795163220783177417589 316
UVM_ERROR @ 3281.690382 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3281.690382 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 53466536021589751133276535007818935146806798644466416250363808310738337168137 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_walkthrough_prod 34127694071995860440005109246832483763066735214134546231655840776879059090139 308
UVM_INFO @ 26383.620884 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 19062119331909798829080173628049495286448160918298594766524723198232809006638 316
UVM_ERROR @ 6920.480920 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6920.480920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 82982556941492971280434347489962282786965863264683173269094099869866520730189 332
UVM_INFO @ 35647.933625 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:387)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 107759950367229149386692564556376969905351538402312120749735310352997972717905 307
UVM_INFO @ 2495.926650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 25224922387571528227689559035142605770330844317235654634829782421693259334011 308
UVM_INFO @ 3409.646194 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 59873948548842716354182819848822364573000103253066826537394274323172028532239 None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
chip_tl_errors 406891247657729315810049417764446368161119086182113257215481524853909952192 217
TL item was: req: (cip_tl_seq_item@43226) { a_addr: 'h10514 a_data: 'h7968ee38 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1f a_opcode: 'h4 a_user: 'h1bad0 d_param: 'h0 d_source: 'h1f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1948.576765 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 434413477663217137917768811859330879733658619305611413642444528710618645138 343
UVM_INFO @ 3777.858312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: * 1 test run
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 12667703720992146887344959033593363887749141690314918185637677966065584739944 316
UVM_INFO @ 7011.977955 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. 1 test run
chip_sw_rv_dm_access_after_wakeup 69504621066154868792748719843608983790207219930997521244807514692127502316308 329
UVM_INFO @ 13177.041773 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_idle_load 102445513398795098922256546428052131803865623174791129306838050087013685525497 318
UVM_INFO @ 15058.631013 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_sleep_load 34718618349296410449632471481622760687463855776938175069278188253696328135421 329
UVM_INFO @ 14817.200228 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 114516961164773057784852801714812188885267156721791959763800156461896673731671 327
UVM_INFO @ 10020.493995 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 70062621286384660701484674520479121633512749153610378205428241814803959186795 272
UVM_INFO @ 10010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_exception_c 65352351340932622696291107131436595055349469936900824364494956670371371745991 319
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 6628.657065 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_output 48037539664534105724595374502062746956611354435368817773424012909720067282249 312
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 8603.853001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 97875379810688383796990901480345138901491035032336129826096218618444208726635 325
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 21190015635807419637274070494332917180438003853119913674915921478012159917906 326
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_no_meas 58114370080378490747850515591166736098455649743780905703378319686127695476379 319
UVM_INFO @ 15591.544088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_invalid_meas 42376383633076388942134144633194714444259193384157233444654419471112358932257 319
UVM_INFO @ 15695.082688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 100818662284105367422187973676181732828991433429488569078621986147122702925535 327
UVM_ERROR @ 4806.746300 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4806.746300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---